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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-25 14:43:26 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-25 14:43:26 +0300 |
| commit | b66364ada279c1fb81583003001b332dd4521f93 (patch) | |
| tree | 7e5c533b67f7478a43cc06f27c0a29b2f77db3dd /tests | |
| parent | fc6ebf8268780c47b503e68be4b2ec368388e2c5 (diff) | |
| download | yosys-b66364ada279c1fb81583003001b332dd4521f93.tar.gz yosys-b66364ada279c1fb81583003001b332dd4521f93.tar.bz2 yosys-b66364ada279c1fb81583003001b332dd4521f93.zip | |
Change sync controls to async.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ice40/adffs.v | 8 | ||||
| -rw-r--r-- | tests/ice40/adffs.ys | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index 05e68caf7..09dc36001 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -27,7 +27,7 @@ module dffs initial begin q = 0; end - always @( posedge clk ) + always @( posedge clk, posedge pre ) if ( pre ) q <= 1'b1; else @@ -39,9 +39,9 @@ module ndffnr initial begin q = 0; end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; + always @( negedge clk, negedge pre ) + if ( !pre ) + q <= 1'b1; else q <= d; endmodule diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index f82da6b14..548060b66 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -4,8 +4,8 @@ flatten equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFFNSR +select -assert-count 1 t:SB_DFFNS select -assert-count 2 t:SB_DFFR -select -assert-count 1 t:SB_DFFSS -select -assert-count 1 t:SB_LUT4 -select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D +select -assert-count 1 t:SB_DFFS +select -assert-count 2 t:SB_LUT4 +select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D |