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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 17:20:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 17:20:39 -0700 |
| commit | 369652d4b99181e2f7b875b6c458c1a5a3b0381e (patch) | |
| tree | a3e032e4c03104a8951c56c83f27767cf38d0aa8 /tests | |
| parent | edc378072301dba7ee79dd1d64a825faf72a1d62 (diff) | |
| download | yosys-369652d4b99181e2f7b875b6c458c1a5a3b0381e.tar.gz yosys-369652d4b99181e2f7b875b6c458c1a5a3b0381e.tar.bz2 yosys-369652d4b99181e2f7b875b6c458c1a5a3b0381e.zip | |
Add test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/techmap/techmap_replace.ys | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys new file mode 100644 index 000000000..ee5c6bc7e --- /dev/null +++ b/tests/techmap/techmap_replace.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module sub(input i, output o, input j); +foobar _TECHMAP_REPLACE_(i, o, j); +wire _TECHMAP_REPLACE_.asdf = i ; +endmodule +EOT +design -stash techmap + +read_verilog <<EOT +module top(input i, output o); +sub s0(i, o); +endmodule +EOT + +techmap -map %techmap +select -assert-any w:s0.asdf |