Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Remove leftover comment | Eddie Hung | 2019-06-20 | 1 | -3/+0 |
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* | Add test | Eddie Hung | 2019-06-20 | 1 | -0/+24 |
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* | Update some .gitignore files | Clifford Wolf | 2019-06-20 | 2 | -3/+3 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add proper test for SV-style arrays | Clifford Wolf | 2019-06-20 | 3 | -6/+16 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵ | Clifford Wolf | 2019-06-20 | 2 | -0/+6 |
|\ | | | | | | | towoe-unpacked_arrays | ||||
| * | Unpacked array declaration using size | Tobias Wölfel | 2019-06-19 | 2 | -0/+6 |
| | | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work. | ||||
* | | Merge pull request #1105 from YosysHQ/clifford/fixlogicinit | Clifford Wolf | 2019-06-19 | 2 | -14/+37 |
|\ \ | | | | | | | Improve handling of initial/default values | ||||
| * | | Add defvalue test, minor autotest fixes for .sv files | Clifford Wolf | 2019-06-19 | 2 | -14/+37 |
| |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* / | Make tests/aiger less chatty | Clifford Wolf | 2019-06-19 | 1 | -4/+6 |
|/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add some more comments | Eddie Hung | 2019-06-10 | 1 | -1/+6 |
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* | Test *.aag too, by using *.aig as reference | Eddie Hung | 2019-06-07 | 1 | -0/+19 |
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* | Use ABC to convert from AIGER to Verilog | Eddie Hung | 2019-06-07 | 1 | -2/+3 |
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* | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 |
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* | Add symbols to AIGER test inputs for ABC | Eddie Hung | 2019-06-07 | 22 | -8/+40 |
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* | Merge pull request #1077 from YosysHQ/clifford/pr983 | Clifford Wolf | 2019-06-07 | 2 | -0/+31 |
|\ | | | | | elaboration system tasks | ||||
| * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵ | Clifford Wolf | 2019-06-07 | 2 | -0/+31 |
| |\ | | | | | | | | | | clifford/pr983 | ||||
| | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 2 | -0/+31 |
| | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen. | ||||
* | | | Rename implicit_ports.sv test to implicit_ports.v | Clifford Wolf | 2019-06-07 | 1 | -0/+0 |
|/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 2 | -12/+1 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵ | Clifford Wolf | 2019-06-07 | 4 | -3/+42 |
|\ \ | | | | | | | | | | into tux3-implicit_named_connection | ||||
| * | | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 4 | -3/+42 |
| | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005. | ||||
* | | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵ | Maciej Kurc | 2019-06-04 | 4 | -0/+46 |
| | | | | | | | | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | | | Added tests for attributes | Maciej Kurc | 2019-06-03 | 9 | -0/+219 |
|/ / | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | | Merge pull request #1049 from YosysHQ/clifford/fix1047 | Clifford Wolf | 2019-05-28 | 1 | -0/+4 |
|\ \ | | | | | | | Do not use shiftmul peepopt pattern when mul result is truncated | ||||
| * | | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 | Clifford Wolf | 2019-05-28 | 1 | -0/+4 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Add actual wandwor test that is part of "make test" | Clifford Wolf | 2019-05-28 | 2 | -33/+36 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 2 | -0/+76 |
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| * | | Fix init | Eddie Hung | 2019-05-24 | 1 | -27/+27 |
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| * | | Fix typos | Eddie Hung | 2019-05-24 | 1 | -6/+6 |
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| * | | Add more tests | Eddie Hung | 2019-05-24 | 2 | -20/+41 |
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| * | | Call proc | Eddie Hung | 2019-05-24 | 1 | -1/+1 |
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| * | | Fix duplicate driver | Eddie Hung | 2019-05-24 | 1 | -15/+15 |
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| * | | Add opt_rmdff tests | Eddie Hung | 2019-05-23 | 2 | -0/+55 |
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* | | | reformat wand/wor test | Stefan Biereigel | 2019-05-27 | 1 | -22/+21 |
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* | | | remove port direction workaround from test case | Stefan Biereigel | 2019-05-27 | 1 | -2/+1 |
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* | | | add simple test case for wand/wor | Stefan Biereigel | 2019-05-23 | 1 | -0/+35 |
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* | | Added tests for Verilog frontent for attributes on parameters and localparams | Maciej Kurc | 2019-05-16 | 2 | -0/+22 |
| | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
* | | Add test case from #997 | Clifford Wolf | 2019-05-07 | 1 | -0/+12 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 2 | -0/+86 |
|\ \ | | | | | | | Add specify parser | ||||
| * | | Improve tests/various/specify.ys | Clifford Wolf | 2019-05-06 | 1 | -2/+32 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | More testing | Eddie Hung | 2019-05-03 | 2 | -2/+5 |
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| * | | Fix spacing | Eddie Hung | 2019-05-03 | 1 | -6/+6 |
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| * | | Add quick-and-dirty specify tests | Eddie Hung | 2019-05-03 | 2 | -0/+53 |
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* | | | Merge pull request #975 from YosysHQ/clifford/fix968 | Clifford Wolf | 2019-05-06 | 1 | -0/+25 |
|\ \ \ | | | | | | | | | Re-enable "final loop assignment" feature and fix opt_clean warnings | ||||
| * | | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 | Clifford Wolf | 2019-05-06 | 6 | -5/+60 |
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| * | | | Add additional test cases for for-loops | Clifford Wolf | 2019-05-01 | 1 | -0/+25 |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | | Merge pull request #871 from YosysHQ/verific_import | Clifford Wolf | 2019-05-06 | 1 | -0/+52 |
|\ \ \ \ | |_|/ / |/| | | | Improve verific -chparam and add hierarchy -chparam | ||||
| * | | | Add tests/various/chparam.sh | Clifford Wolf | 2019-05-06 | 1 | -0/+52 |
| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | | iverilog with simcells.v as well | Eddie Hung | 2019-05-03 | 1 | -1/+2 |
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* | | | | Merge pull request #969 from YosysHQ/clifford/pmgenstuff | Clifford Wolf | 2019-05-03 | 1 | -0/+9 |
|\ \ \ \ | |/ / / |/| | | | Improve pmgen, Add "peepopt" pass with shift-mul pattern |