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Author
Age
Files
Lines
*
From master
Eddie Hung
2019-05-28
1
-1
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+1
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-05-21
1
-1
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+2
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iverilog with simcells.v as well
Eddie Hung
2019-05-03
1
-1
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+2
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Merge remote-tracking branch 'origin/xc7srl' into xc7mux
Eddie Hung
2019-04-22
1
-2
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+2
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Fix tests
Clifford Wolf
2019-04-21
1
-2
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+2
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Merge branch 'master' into xaig
Eddie Hung
2019-04-08
1
-3
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+3
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Merge https://github.com/YosysHQ/yosys into read_aiger
Eddie Hung
2019-03-19
1
-7
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+5
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Hotfix for "make test"
Clifford Wolf
2019-02-28
1
-1
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+1
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Add "write_verilog -siminit"
Clifford Wolf
2019-02-28
1
-1
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+1
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Fix FIRRTL to Verilog process instance subfield assignment.
Jim Lawson
2019-02-25
1
-1
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+1
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One more merge conflict
Eddie Hung
2019-02-17
1
-6
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+1
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Merge https://github.com/YosysHQ/yosys into read_aiger
Eddie Hung
2019-02-17
2
-7
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+46
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Revert "tests/simple to also do LUT synth"
Eddie Hung
2019-02-21
1
-1
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+0
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-02-21
1
-4
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+2
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Revert "Add -B option to autotest.sh to append to backend_opts"
Eddie Hung
2019-02-21
1
-4
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+2
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tests/simple to also do LUT synth
Eddie Hung
2019-02-21
1
-0
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+1
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Merge branch 'master' into xaig
Eddie Hung
2019-02-19
2
-7
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+41
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Merge https://github.com/YosysHQ/yosys into dff_init
Eddie Hung
2019-02-17
2
-7
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+42
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Update cells supported for verilog to FIRRTL conversion.
Jim Lawson
2019-02-15
2
-7
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+42
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Support and differentiate between ASCII and binary AIG testing
Eddie Hung
2019-02-08
1
-1
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+1
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Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig
Eddie Hung
2019-02-06
1
-2
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+4
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Add -B option to autotest.sh to append to backend_opts
Eddie Hung
2019-02-06
1
-2
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+4
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Revert most of autotest.sh; for non *.v use Yosys to translate
Eddie Hung
2019-02-06
1
-7
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+9
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Add tests
Eddie Hung
2019-02-04
1
-8
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+13
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Fixed typo (sikp -> skip)
Udi Finkelstein
2018-06-05
1
-1
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+1
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autotest.sh: Change from /bin/bash to /usr/bin/env bash
Johnny Sorocil
2018-05-06
1
-1
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+1
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Merge branch 'master' of https://github.com/brouhaha/yosys
Clifford Wolf
2016-09-23
1
-1
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+6
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Add optional SEED=n command line option to Makefile, and -S n command line op...
Eric Smith
2016-09-22
1
-1
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+6
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Added autotest.sh -I
Clifford Wolf
2016-09-20
1
-16
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+19
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Fix for modules with big interfaces.
Kaj Tuomi
2016-09-13
1
-2
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+2
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Added "test_autotb -seed" (and "autotest.sh -S")
Clifford Wolf
2016-08-06
1
-2
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+4
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Fixed autotest.sh handling of `timescale
Clifford Wolf
2016-07-02
1
-14
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+10
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Improvements and fixes in autotest.sh script and test_autotb
Clifford Wolf
2016-05-20
1
-6
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+6
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Fix for Modelsim transcript line warp issue #164
Kaj Tuomi
2016-05-19
1
-4
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+4
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Optionally use ${CC} when compiling test utils.
Sergey Kvachonok
2016-03-25
1
-1
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+1
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Switched to Python 3
Clifford Wolf
2015-08-22
1
-4
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+1
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Another block of spelling fixes
Larry Doolittle
2015-08-14
1
-1
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+1
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Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
1
-1
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+1
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Some test related fixes
Clifford Wolf
2015-02-12
1
-1
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+1
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Refactoring of memory_bram and xilinx brams
Clifford Wolf
2015-01-18
1
-0
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+2
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Tiny fix in vcdcd.pl
Clifford Wolf
2015-01-13
1
-2
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+2
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Added "synth" command
Clifford Wolf
2014-09-14
1
-2
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+2
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Fixed autotest for non-basename arguments
Clifford Wolf
2014-09-06
1
-0
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+3
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Added autotest -e (do not use -noexpr on write_verilog)
Clifford Wolf
2014-08-30
1
-2
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+4
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Added "wreduce" to some of the standard test benches
Clifford Wolf
2014-08-03
1
-1
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+1
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Added "test_autotb -n <num_iter>" option
Clifford Wolf
2014-08-01
1
-2
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+5
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Added "make -j{N}" support to "make test"
Clifford Wolf
2014-07-30
2
-6
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+23
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Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
Clifford Wolf
2014-07-29
1
-1
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+1
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Added "opt_const -fine" and "opt_reduce -fine"
Clifford Wolf
2014-07-21
1
-1
/
+1
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Also simulate unmapped memories in "make test"
Clifford Wolf
2014-07-17
1
-1
/
+1
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