| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | verific: Use new value change logic also for $stable of wide signals. | Jannis Harder | 2022-05-11 | 2 | -2/+43 |
| | | | | | I missed this in the previous PR. | ||||
| * | Merge pull request #3305 from jix/sva_value_change_logic | Jannis Harder | 2022-05-09 | 7 | -1/+96 |
| |\ | | | | | verific: Improve logic generated for SVA value change expressions | ||||
| | * | verific: Improve logic generated for SVA value change expressions | Jannis Harder | 2022-05-09 | 7 | -1/+96 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previously generated logic assumed an unconstrained past value in the initial state and did not handle 'x values. While the current formal verification flow uses 2-valued logic, SVA value change expressions require a past value of 'x during the initial state to behave in the expected way (i.e. to consider both an initial 0 and an initial 1 as $changed and an initial 1 as $rose and an initial 0 as $fell). This patch now generates logic that at the same time a) provides the expected behavior in a 2-valued logic setting, not depending on any dont-care optimizations, and b) properly handles 'x values in yosys simulation | ||||
| * | | Merge pull request #3297 from jix/sva_nested_clk_else | Jannis Harder | 2022-05-09 | 1 | -0/+11 |
| |\ \ | |/ |/| | verific: Fix conditions of SVAs with explicit clocks within procedures | ||||
| | * | verific: Fix conditions of SVAs with explicit clocks within procedures | Jannis Harder | 2022-05-03 | 1 | -0/+11 |
| | | | | | | | | | | | | | | | | | | | For SVAs that have an explicit clock and are contained in a procedure which conditionally executes the assertion, verific expresses this using a mux with one input connected to constant 1 and the other output connected to an SVA_AT. The existing code only handled the case where the first input is connected to 1. This patch also handles the other case. | ||||
| * | | Fix running sva tests | Miodrag Milanovic | 2022-05-09 | 1 | -4/+3 |
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| * | Fix "verific -extnets" for more complex situations | Clifford Wolf | 2019-03-26 | 1 | -0/+22 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Squelch a little more trailing whitespace | Larry Doolittle | 2018-12-29 | 1 | -1/+1 |
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| * | Major redesign of Verific SVA importer | Clifford Wolf | 2018-02-27 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add support for SVA throughout via Verific | Clifford Wolf | 2018-02-21 | 1 | -1/+1 |
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| * | Add support for SVA sequence concatenation ranges via verific | Clifford Wolf | 2018-02-18 | 2 | -0/+20 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add support for SVA until statements via Verific | Clifford Wolf | 2018-02-18 | 1 | -0/+19 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF | Clifford Wolf | 2018-02-15 | 1 | -0/+34 |
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| * | Remove PSL example from tests/sva/ | Clifford Wolf | 2017-10-20 | 2 | -35/+1 |
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| * | Add simple VHDL+PSL example | Clifford Wolf | 2017-07-28 | 4 | -17/+64 |
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| * | Improve Verific SVA importer | Clifford Wolf | 2017-07-27 | 1 | -7/+8 |
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| * | Add counter.sv SVA test | Clifford Wolf | 2017-07-27 | 1 | -0/+29 |
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| * | Improve SVA tests, add Makefile and scripts | Clifford Wolf | 2017-07-27 | 11 | -9/+110 |
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| * | Add more SVA test cases for future Verific work | Clifford Wolf | 2017-07-22 | 5 | -1/+74 |
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| * | Add some simple SVA test cases for future Verific work | Clifford Wolf | 2017-07-22 | 4 | -0/+45 |
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index : iCE40/yosys | |
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