| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix "verific -extnets" for more complex situations | Clifford Wolf | 2019-03-26 | 1 | -0/+22 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Squelch a little more trailing whitespace | Larry Doolittle | 2018-12-29 | 1 | -1/+1 |
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| * | Major redesign of Verific SVA importer | Clifford Wolf | 2018-02-27 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add support for SVA throughout via Verific | Clifford Wolf | 2018-02-21 | 1 | -1/+1 |
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| * | Add support for SVA sequence concatenation ranges via verific | Clifford Wolf | 2018-02-18 | 2 | -0/+20 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add support for SVA until statements via Verific | Clifford Wolf | 2018-02-18 | 1 | -0/+19 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF | Clifford Wolf | 2018-02-15 | 1 | -0/+34 |
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| * | Remove PSL example from tests/sva/ | Clifford Wolf | 2017-10-20 | 2 | -35/+1 |
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| * | Add simple VHDL+PSL example | Clifford Wolf | 2017-07-28 | 4 | -17/+64 |
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| * | Improve Verific SVA importer | Clifford Wolf | 2017-07-27 | 1 | -7/+8 |
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| * | Add counter.sv SVA test | Clifford Wolf | 2017-07-27 | 1 | -0/+29 |
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| * | Improve SVA tests, add Makefile and scripts | Clifford Wolf | 2017-07-27 | 11 | -9/+110 |
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| * | Add more SVA test cases for future Verific work | Clifford Wolf | 2017-07-22 | 5 | -1/+74 |
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| * | Add some simple SVA test cases for future Verific work | Clifford Wolf | 2017-07-22 | 4 | -0/+45 |
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index : iCE40/yosys | |
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