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| * | Simplify breaking tests/arch/*/fsm.ys testsEddie Hung2020-03-202-7/+3
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* | | fix argument order for macOS compatibilityN. Engelhardt2020-03-181-3/+3
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* | tests: extend tests/arch/run-tests.sh for definesEddie Hung2020-03-051-3/+14
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* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-2/+2
|\ \ | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * | Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
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* | | Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"Eddie Hung2020-02-271-3/+9
| | | | | | | | | | | | This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
* | | Cleanup testsEddie Hung2020-02-271-0/+18
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* | | Update bug1630.ys to use -lut 4 instead of lut fileEddie Hung2020-02-271-1/+1
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* | | Fix tests/arch/xilinx/fsm.ys to count flops onlyEddie Hung2020-02-271-9/+3
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* | xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-071-0/+20
| | | | | | | | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* | xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-1/+83
|/ | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* Merge pull request #1650 from YosysHQ/eddie/shiftx2muxEddie Hung2020-02-052-5/+5
|\ | | | | techmap LSB-first for compatible $shift/$shiftx cells
| * Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-057-28/+173
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| * | Update tests with reduced areaEddie Hung2020-01-212-6/+6
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* | | abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-051-1/+21
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* | Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-033-4/+61
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* | Merge pull request #1559 from YosysHQ/efinix_test_fixMiodrag Milanović2020-01-291-1/+1
|\ \ | | | | | | Fix for non-deterministic test
| * | Updated test to use assert-maxMiodrag Milanovic2020-01-281-1/+1
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| * | Fix for non-deterministic testMiodrag Milanovic2019-12-071-1/+1
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* | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_lutsEddie Hung2020-01-282-0/+102
|\ \ \ | | | | | | | | Unpermute LUT ordering for ice40/ecp5/xilinx
| * | | Import tests from #1628Eddie Hung2020-01-272-0/+102
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* | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+5
|\ \ \ \ | |/ / / |/| | | synth_xilinx: error out if tristate without '-iopad'
| * | | Add testEddie Hung2019-12-121-0/+5
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* | | | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3Eddie Hung2020-01-241-23/+4
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* | | xilinx_dsp: another typo; move xilinx specific testEddie Hung2020-01-171-0/+11
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* | | ice40_dsp: fix typoEddie Hung2020-01-171-0/+11
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* | | Add #1644 testcaseEddie Hung2020-01-172-0/+2
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* | | ice40_dsp: add testEddie Hung2020-01-171-0/+11
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* | | Merge pull request #1632 from YosysHQ/eddie/fix1630Eddie Hung2020-01-142-0/+2
|\ \ \ | | | | | | | | read_aiger: uniquify wires with $aiger<autoidx> prefix
| * | | Add #1630 testcaseEddie Hung2020-01-132-0/+2
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* | | | Merge pull request #1623 from YosysHQ/mmicko/edif_attrMiodrag Milanović2020-01-143-9/+8
|\ \ \ \ | |/ / / |/| | | Export wire properties in EDIF
| * | | this one is fineMiodrag Milanovic2020-01-101-3/+3
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| * | | Fix testsMiodrag Milanovic2020-01-103-12/+11
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* | | | Add #1626 testcaseEddie Hung2020-01-121-0/+217
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* | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_mfsEddie Hung2020-01-072-0/+123
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| * | | Combine tests to check multiple clock domainsEddie Hung2020-01-021-33/+10
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-0210-11/+31
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| * | | | Add some abc9 dff testsEddie Hung2019-12-311-0/+55
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| * | | | Add -D DFF_MODE to abc9_map testEddie Hung2019-12-301-4/+4
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3024-57/+224
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| * \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1920-66/+750
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| * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-123-23/+136
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| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-064-3/+302
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| * | | | | | abc9_map.v to transform INIT=1 to INIT=0Eddie Hung2019-12-041-0/+91
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* | | | | | | Add testcase from #1459Eddie Hung2020-01-061-0/+25
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* | | | | | Merge pull request #1606 from YosysHQ/eddie/improve_testsEddie Hung2020-01-019-11/+12
|\ \ \ \ \ \ | | | | | | | | | | | | | | Fix a few issues in tests/arch/*
| * | | | | | Revert insertion of 'reg', leave note behindEddie Hung2020-01-011-1/+2
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| * | | | | | Do not do call equiv_opt when no sim model existsEddie Hung2019-12-312-4/+4
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| * | | | | | Fix warningsEddie Hung2019-12-312-2/+2
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| * | | | | | Call equiv_opt with -multiclock and -assertEddie Hung2019-12-315-5/+5
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