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| author | Claire Wolf <clifford@clifford.at> | 2020-03-03 08:38:32 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-03 08:38:32 -0800 |
| commit | b597f85b13b5369398350ef4ef43b7b2521eb140 (patch) | |
| tree | 18ea3d52b5927ea1491162458e16cfcfd3280418 /tests/arch | |
| parent | 91892465e1af2bcb5ec348b86ba4e566b040cb12 (diff) | |
| parent | f80fe8dc22ca2b3639b7b0bbff69458addb05432 (diff) | |
| download | yosys-b597f85b13b5369398350ef4ef43b7b2521eb140.tar.gz yosys-b597f85b13b5369398350ef4ef43b7b2521eb140.tar.bz2 yosys-b597f85b13b5369398350ef4ef43b7b2521eb140.zip | |
Merge pull request #1718 from boqwxp/precise_locations
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/ice40/ice40_wrapcarry.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/ice40/ice40_wrapcarry.ys b/tests/arch/ice40/ice40_wrapcarry.ys index fb9fccc3a..74319c480 100644 --- a/tests/arch/ice40/ice40_wrapcarry.ys +++ b/tests/arch/ice40/ice40_wrapcarry.ys @@ -50,5 +50,5 @@ select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d select -assert-count 1 a:keep=1 a:SB_CARRY.\foo=bar %i a:SB_CARRY.\answer=42 %i a:SB_LUT4.\blah=blah %i a:SB_LUT4.\answer=43 %i ice40_wrapcarry -unwrap -select -assert-count 1 c:carry a:src=<<EOT:3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i -select -assert-count 1 c:adder a:src=<<EOT:10 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i +select -assert-count 1 c:carry a:src=<<EOT:3.11-8.3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i +select -assert-count 1 c:adder a:src=<<EOT:12.4-18.3 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i |