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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-17 17:07:03 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-17 17:07:03 -0800 |
| commit | 6a163b5ddd378ba847054ad9226af8ca569c977a (patch) | |
| tree | 10fadff3585ad4c56a2a0fcefcf44f9e6e36eefe /tests/arch | |
| parent | db68e4c2a7a39eda46863fba8b8c8313a831f606 (diff) | |
| download | yosys-6a163b5ddd378ba847054ad9226af8ca569c977a.tar.gz yosys-6a163b5ddd378ba847054ad9226af8ca569c977a.tar.bz2 yosys-6a163b5ddd378ba847054ad9226af8ca569c977a.zip | |
xilinx_dsp: another typo; move xilinx specific test
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/xilinx/bug1462.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/arch/xilinx/bug1462.ys b/tests/arch/xilinx/bug1462.ys new file mode 100644 index 000000000..15cab5121 --- /dev/null +++ b/tests/arch/xilinx/bug1462.ys @@ -0,0 +1,11 @@ +read_verilog << EOF +module top(...); +input wire [31:0] A; +output wire [31:0] P; + +assign P = A * 32'h12300000; + +endmodule +EOF + +synth_xilinx |