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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 16:16:05 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 16:16:05 -0800 |
| commit | ccc0a740d254e6895b49037681bc484d6572342d (patch) | |
| tree | ac883acc4a66184a92c94ddd54bc79332043ff77 /tests/arch | |
| parent | cac7f5d82eb2760bcc248d15315b0d8460c92cb0 (diff) | |
| download | yosys-ccc0a740d254e6895b49037681bc484d6572342d.tar.gz yosys-ccc0a740d254e6895b49037681bc484d6572342d.tar.bz2 yosys-ccc0a740d254e6895b49037681bc484d6572342d.zip | |
Add some abc9 dff tests
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/xilinx/abc9_dff.ys | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys new file mode 100644 index 000000000..6611b4f18 --- /dev/null +++ b/tests/arch/xilinx/abc9_dff.ys @@ -0,0 +1,55 @@ +read_verilog <<EOT +module top(input C, D, output [3:0] Q); +FDRE fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0])); +FDSE fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1])); +FDCE fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2])); +FDPE fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3])); +endmodule +EOT +equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf +design -load postopt +select -assert-none t:FD* + + +design -reset +read_verilog <<EOT +module top(input C, D, output [3:0] Q); +FDRE fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0])); +FDSE fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1])); +FDCE fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2])); +FDPE fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3])); +endmodule +EOT +equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf +design -load postopt +select -assert-none t:FD* + + +design -reset +read_verilog <<EOT +module top(input C, D, output [3:0] Q); +FDRE_1 fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0])); +FDSE_1 fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1])); +FDCE_1 fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2])); +FDPE_1 fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3])); +endmodule +EOT + +equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf +design -load postopt +select -assert-none t:FD* + + +design -reset +read_verilog <<EOT +module top(input C, D, output [3:0] Q); +FDRE_1 fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0])); +FDSE_1 fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1])); +FDCE_1 fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2])); +FDPE_1 fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3])); +endmodule +EOT + +equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf +design -load postopt +select -assert-none t:FD* |