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Author
Age
Files
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tests: update fsm.ys resource count
Eddie Hung
2020-07-04
1
-4
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+4
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intel_alm: fix DFFE matching
Dan Ravensloft
2020-06-11
2
-4
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+4
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Add missing .gitignore file
Claire Wolf
2020-06-04
1
-0
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+2
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Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
Eddie Hung
2020-06-04
1
-4
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+53
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abc9_ops: update messaging (credit to @Xiretza for spotting)
Eddie Hung
2020-05-30
1
-4
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+4
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tests: add test for abc9 -dff removing a redundant flop entirely
Eddie Hung
2020-05-25
1
-0
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+15
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tests: add testcase for abc9 -dff preserving flop names
Eddie Hung
2020-05-25
1
-0
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+34
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Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
Eddie Hung
2020-06-03
1
-0
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+13
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tests: tidy up testcase
Eddie Hung
2020-06-03
1
-3
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+0
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tests: add ecp5 latch testcase with -abc9
Eddie Hung
2020-05-25
1
-0
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+16
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Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings
Eddie Hung
2020-06-03
2
-2
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+2
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tests: fix some test warnings
Eddie Hung
2020-05-25
2
-2
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+2
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allow range for mux test
Miodrag Milanovic
2020-06-01
1
-1
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+2
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tests: xilinx macc test to have initval, shorten BMC depth for runtime
Eddie Hung
2020-05-25
2
-8
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+8
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Add force_downto and force_upto wire attributes.
Marcelina Kościelnicka
2020-05-19
1
-2
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+4
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abc9_ops: add -prep_bypass for auto bypass boxes; refactor
Eddie Hung
2020-05-14
1
-5
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+29
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abc9: suppress warnings when no compatible + used flop boxes formed
Eddie Hung
2020-05-14
1
-1
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+3
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xilinx: update abc9_dff tests
Eddie Hung
2020-05-14
1
-18
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+45
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xilinx: remove no-longer-relevant test
Eddie Hung
2020-05-14
1
-91
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+0
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intel_alm: direct LUTRAM cell instantiation
Dan Ravensloft
2020-05-07
1
-0
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+20
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intel_alm: work around a Quartus ICE
Dan Ravensloft
2020-04-23
1
-0
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+12
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tests: read +/xilinx/cell_sim.v before xilinx_dsp test
Eddie Hung
2020-04-22
1
-0
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+1
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test: ice40_dsp test to read +/ice40/cells_sim.v for default params
Eddie Hung
2020-04-22
1
-0
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+1
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xilinx: xilinx_dffopt to read cells_sim.v; fix test
Eddie Hung
2020-04-22
1
-13
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+22
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tests: remove write_ilang
Eddie Hung
2020-04-20
2
-3
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+0
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synth_intel_alm: alternative synthesis for Intel FPGAs
Dan Ravensloft
2020-04-15
10
-0
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+208
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Merge pull request #1603 from whitequark/ice40-ram_style
whitequark
2020-04-10
5
-35
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+551
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ecp5: do not map FFRAM if explicitly requested otherwise.
whitequark
2020-04-03
1
-16
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+62
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ice40: do not map FFRAM if explicitly requested otherwise.
whitequark
2020-04-03
1
-8
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+28
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ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
whitequark
2020-02-06
3
-5
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+305
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ice40: match memory inference attribute values case insensitive.
whitequark
2020-02-06
1
-0
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+6
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ice40: add support for both 1364.1 and LSE RAM/ROM attributes.
whitequark
2020-02-06
3
-20
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+179
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ice40: remove impossible test.
whitequark
2020-02-06
1
-15
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+0
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Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
Eddie Hung
2020-04-01
2
-7
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+3
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Simplify breaking tests/arch/*/fsm.ys tests
Eddie Hung
2020-03-20
2
-7
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+3
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fix argument order for macOS compatibility
N. Engelhardt
2020-03-18
1
-3
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+3
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tests: extend tests/arch/run-tests.sh for defines
Eddie Hung
2020-03-05
1
-3
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+14
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Merge pull request #1718 from boqwxp/precise_locations
Claire Wolf
2020-03-03
1
-2
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+2
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Change attribute search value to specify precise location instead of simple l...
Alberto Gonzalez
2020-02-24
1
-2
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+2
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Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"
Eddie Hung
2020-02-27
1
-3
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+9
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Cleanup tests
Eddie Hung
2020-02-27
1
-0
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+18
*
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Update bug1630.ys to use -lut 4 instead of lut file
Eddie Hung
2020-02-27
1
-1
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+1
*
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Fix tests/arch/xilinx/fsm.ys to count flops only
Eddie Hung
2020-02-27
1
-9
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+3
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*
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xilinx: Add support for LUT RAM on LUT4-based devices.
Marcin Kościelnicki
2020-02-07
1
-0
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+20
*
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xilinx: Initial support for LUT4 devices.
Marcin Kościelnicki
2020-02-07
3
-1
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+83
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Merge pull request #1650 from YosysHQ/eddie/shiftx2mux
Eddie Hung
2020-02-05
2
-5
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+5
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Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
Eddie Hung
2020-02-05
7
-28
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+173
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Update tests with reduced area
Eddie Hung
2020-01-21
2
-6
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+6
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abc9_ops: -reintegrate to use derived_type for box_ports
Eddie Hung
2020-02-05
1
-1
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+21
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Add opt_lut_ins pass. (#1673)
Marcelina Kościelnicka
2020-02-03
3
-4
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+61
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