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* Tests for ram_style = "huge"KrystalDelusion2023-02-212-0/+182
* Asymmetric port ram tests with XilinxKrystalDelusion2023-02-213-0/+193
* Fix tests for check in equiv_optJannis Harder2022-10-073-6/+14
* xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-46/+15
* Fix the tests we just brokeClaire Xenia Wolf2021-12-101-2/+2
* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-2/+3
* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-3/+3
* xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-272-1/+48
* xilinx: Fix attributes_test.ysMarcelina Kościelnicka2020-10-241-4/+2
* Merge pull request #2380 from Xiretza/parallel-testsclairexen2020-10-011-19/+3
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| * tests: Centralize test collection and Makefile generationXiretza2020-09-211-19/+3
* | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-231-0/+37
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* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-311-2/+1
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-9/+7
* satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-241-2/+0
* xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-0/+41
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-4/+53
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| * abc9_ops: update messaging (credit to @Xiretza for spotting)Eddie Hung2020-05-301-4/+4
| * tests: add test for abc9 -dff removing a redundant flop entirelyEddie Hung2020-05-251-0/+15
| * tests: add testcase for abc9 -dff preserving flop namesEddie Hung2020-05-251-0/+34
* | Merge pull request #2080 from YosysHQ/eddie/fix_test_warningsEddie Hung2020-06-032-2/+2
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| * | tests: fix some test warningsEddie Hung2020-05-252-2/+2
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* / tests: xilinx macc test to have initval, shorten BMC depth for runtimeEddie Hung2020-05-252-8/+8
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-191-2/+4
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-5/+29
* abc9: suppress warnings when no compatible + used flop boxes formedEddie Hung2020-05-141-1/+3
* xilinx: update abc9_dff testsEddie Hung2020-05-141-18/+45
* xilinx: remove no-longer-relevant testEddie Hung2020-05-141-91/+0
* tests: read +/xilinx/cell_sim.v before xilinx_dsp testEddie Hung2020-04-221-0/+1
* xilinx: xilinx_dffopt to read cells_sim.v; fix testEddie Hung2020-04-221-13/+22
* fix argument order for macOS compatibilityN. Engelhardt2020-03-181-3/+3
* Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"Eddie Hung2020-02-271-3/+9
* Cleanup testsEddie Hung2020-02-271-0/+18
* Fix tests/arch/xilinx/fsm.ys to count flops onlyEddie Hung2020-02-271-9/+3
* xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-071-0/+20
* xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-1/+83
* abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-051-1/+21
* Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+25
* Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+5
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| * Add testEddie Hung2019-12-121-0/+5
* | xilinx_dsp: another typo; move xilinx specific testEddie Hung2020-01-171-0/+11
* | ice40_dsp: fix typoEddie Hung2020-01-171-0/+11
* | this one is fineMiodrag Milanovic2020-01-101-3/+3
* | Fix testsMiodrag Milanovic2020-01-103-12/+11
* | Combine tests to check multiple clock domainsEddie Hung2020-01-021-33/+10
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-0/+19
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| * | Added a test caseMiodrag Milanovic2020-01-011-0/+19
* | | Add some abc9 dff testsEddie Hung2019-12-311-0/+55
* | | Add -D DFF_MODE to abc9_map testEddie Hung2019-12-301-4/+4
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3021-54/+189
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