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* Fix files with CRLF line endingsClaire Xenia Wolf2021-06-093-73/+73
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* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-261-3/+4
| | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
* ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-061-5/+5
| | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-062-20/+53
| | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-162-21/+42
|\ | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M
| * Rename memory tests to lutram, add more xilinx testsEddie Hung2019-12-122-21/+42
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* | Merge blockram testsEddie Hung2019-12-161-0/+0
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* | Fixing compiler warning/issues. Moving test script to the correct placeDiego H2019-12-161-47/+0
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* | Removing fixed attribute value to !ramstyle rulesDiego H2019-12-151-3238/+0
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* | Merging attribute rules into a single match block; Adding testsDiego H2019-12-153-0/+3373
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* | Renaming BRAM memory tests for the sake of uniformityDiego H2019-12-131-0/+0
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* | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-121-0/+45
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* fixed errorMiodrag Milanovic2019-10-181-1/+1
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* Unify verilog styleMiodrag Milanovic2019-10-1811-191/+157
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* Common memory test now sharedMiodrag Milanovic2019-10-181-0/+21
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* Share common testsMiodrag Milanovic2019-10-1811-0/+289
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