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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-08-26 18:44:48 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-26 22:50:16 +0200 |
| commit | 1a07b330f8220ce441cabce2b21633a12434229a (patch) | |
| tree | 4c564ecf2f8ae5585c90756151ad7d15381f5400 /tests/arch/common | |
| parent | 4f2b78e19af3a2d342efe9780e220282b7a3a046 (diff) | |
| download | yosys-1a07b330f8220ce441cabce2b21633a12434229a.tar.gz yosys-1a07b330f8220ce441cabce2b21633a12434229a.tar.bz2 yosys-1a07b330f8220ce441cabce2b21633a12434229a.zip | |
intel_alm: Add multiply signedness to cells
Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.
Diffstat (limited to 'tests/arch/common')
| -rw-r--r-- | tests/arch/common/mul.v | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v index 437a91cfc..baed64fcd 100644 --- a/tests/arch/common/mul.v +++ b/tests/arch/common/mul.v @@ -1,9 +1,10 @@ module top +#(parameter X_WIDTH=6, Y_WIDTH=6, A_WIDTH=12) ( - input [5:0] x, - input [5:0] y, + input [X_WIDTH-1:0] x, + input [Y_WIDTH-1:0] y, - output [11:0] A, + output [A_WIDTH-1:0] A, ); assign A = x * y; endmodule |