ice40: add support for both 1364.1 and LSE RAM/ROM attributes.

This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify appear to interpret attribute values insensitive
    to case. There is currently no way to do this in Yosys (attrmap
    can only change case of attribute names).
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).

2 files changed, 53 insertions, 20 deletions

diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v
index dbc6ca65c..5ed0736d0 100644
--- a/tests/arch/common/blockram.v
+++ b/tests/arch/common/blockram.v
@@ -5,19 +5,20 @@ module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
     input  wire  [ADDRESS_WIDTH-1:0] address_in,
     output wire  [DATA_WIDTH-1:0]    data_out);
 
-   localparam WORD  = (DATA_WIDTH-1);
-   localparam DEPTH = (2**ADDRESS_WIDTH-1);
+  localparam WORD  = (DATA_WIDTH-1);
+  localparam DEPTH = (2**ADDRESS_WIDTH-1);
 
-   reg [WORD:0] data_out_r;
-   reg [WORD:0] memory [0:DEPTH];
+  reg [WORD:0] data_out_r;
+  reg [WORD:0] memory [0:DEPTH];
 
-   always @(posedge clk) begin
-      if (write_enable)
-        memory[address_in] <= data_in;
-      data_out_r <= memory[address_in];
-   end
+  always @(posedge clk) begin
+    if (write_enable)
+      memory[address_in] <= data_in;
+    data_out_r <= memory[address_in];
+  end
+
+  assign data_out = data_out_r;
 
-   assign data_out = data_out_r;
 endmodule // sync_ram_sp
 
 
@@ -28,18 +29,19 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
     input  wire  [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
     output wire  [DATA_WIDTH-1:0]    data_out);
 
-   localparam WORD  = (DATA_WIDTH-1);
-   localparam DEPTH = (2**ADDRESS_WIDTH-1);
+  localparam WORD  = (DATA_WIDTH-1);
+  localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+  reg [WORD:0] data_out_r;
+  reg [WORD:0] memory [0:DEPTH];
 
-   reg [WORD:0] data_out_r;
-   reg [WORD:0] memory [0:DEPTH];
+  always @(posedge clk) begin
+    if (write_enable)
+      memory[address_in_w] <= data_in;
+    data_out_r <= memory[address_in_r];
+  end
 
-   always @(posedge clk) begin
-      if (write_enable)
-        memory[address_in_w] <= data_in;
-      data_out_r <= memory[address_in_r];
-   end
+  assign data_out = data_out_r;
 
-   assign data_out = data_out_r;
 endmodule // sync_ram_sdp
 
diff --git a/tests/arch/common/blockrom.v b/tests/arch/common/blockrom.v
new file mode 100644
index 000000000..6f6c9d946
--- /dev/null
+++ b/tests/arch/common/blockrom.v
@@ -0,0 +1,31 @@
+`default_nettype none
+module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
+	 (input  wire                      clk,
+		input  wire  [ADDRESS_WIDTH-1:0] address_in,
+		output wire  [DATA_WIDTH-1:0]    data_out);
+
+	localparam WORD  = (DATA_WIDTH-1);
+	localparam DEPTH = (2**ADDRESS_WIDTH-1);
+
+	reg [WORD:0] data_out_r;
+	reg [WORD:0] memory [0:DEPTH];
+
+	integer i,j = 16'hACE1;
+	initial
+		for (i = 0; i <= DEPTH; i++) begin
+			// In case this ROM will be implemented in fabric: fill the memory with some data
+			// uncorrelated with the address, or Yosys might see through the ruse and e.g. not
+			// emit any LUTs at all for `memory[i] = i;`, just a latch.
+			memory[i] = j;
+			j = j ^ (j >> 7);
+			j = j ^ (j << 9);
+			j = j ^ (j >> 13);
+		end
+
+	always @(posedge clk) begin
+		data_out_r <= memory[address_in];
+	end
+
+	assign data_out = data_out_r;
+
+endmodule // sync_rom