| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | | | Re-order | Eddie Hung | 2019-09-27 | 2 | -2/+2 | |
| | * | | | | | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 | |
| | * | | | | | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once | Eddie Hung | 2019-09-26 | 1 | -9/+4 | |
| | * | | | | | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 | |
| | * | | | | | select once | Eddie Hung | 2019-09-26 | 2 | -8/+12 | |
| | * | | | | | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 3 | -38/+14 | |
| | * | | | | | mul2dsp.v slice names | Eddie Hung | 2019-09-25 | 1 | -5/+5 | |
| | * | | | | | Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit | Eddie Hung | 2019-09-25 | 1 | -3/+1 | |
| | * | | | | | Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" | Eddie Hung | 2019-09-25 | 1 | -2/+6 | |
| | * | | | | | Revert "No need for $__mul anymore?" | Eddie Hung | 2019-09-25 | 1 | -8/+8 | |
| | * | | | | | Only wreduce on t:$add | Eddie Hung | 2019-09-25 | 1 | -1/+1 | |
| | * | | | | | Remove _TECHMAP_CELLTYPE_ check since all $mul | Eddie Hung | 2019-09-25 | 1 | -6/+2 | |
| | * | | | | | No need for $__mul anymore? | Eddie Hung | 2019-09-25 | 1 | -8/+8 | |
| | * | | | | | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -0/+1 | |
| | * | | | | | Oops. Actually use __NAME__ in ABC_DSP48E1 macro | Eddie Hung | 2019-09-25 | 1 | -1/+1 | |
| | * | | | | | Add (* techmap_autopurge *) to abc_unmap.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 | |
| | * | | | | | Add techmap_autopurge to outputs in abc_map.v too | Eddie Hung | 2019-09-23 | 1 | -11/+11 | |
| | * | | | | | Revert "Add a xilinx_finalise pass" | Eddie Hung | 2019-09-23 | 3 | -87/+0 | |
| | * | | | | | Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect" | Eddie Hung | 2019-09-23 | 1 | -38/+38 | |
| | * | | | | | Revert "Vivado does not like zero width port connections" | Eddie Hung | 2019-09-23 | 1 | -2/+2 | |
| | * | | | | | Vivado does not like zero width port connections | Eddie Hung | 2019-09-23 | 1 | -2/+2 | |
| | * | | | | | Remove (* techmap_autopurge *) from abc_unmap.v since no effect | Eddie Hung | 2019-09-23 | 1 | -38/+38 | |
| | * | | | | | Add a xilinx_finalise pass | Eddie Hung | 2019-09-23 | 3 | -0/+87 | |
| | * | | | | | Grammar | Eddie Hung | 2019-09-20 | 1 | -1/+1 | |
| | * | | | | | Fix signedness bug | Eddie Hung | 2019-09-20 | 1 | -2/+2 | |
| | * | | | | | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 2 | -3/+2 | |
| | * | | | | | Revert "Move mul2dsp before wreduce" | Eddie Hung | 2019-09-20 | 1 | -4/+5 | |
| | * | | | | | Move mul2dsp before wreduce | Eddie Hung | 2019-09-20 | 1 | -5/+4 | |
| | * | | | | | Tidy up, fix undriven | Eddie Hung | 2019-09-19 | 1 | -32/+34 | |
| | * | | | | | $__ABC_REG to have WIDTH parameter | Eddie Hung | 2019-09-19 | 2 | -17/+18 | |
| | * | | | | | Fix DSP48E1 timing by breaking P path if MREG or PREG | Eddie Hung | 2019-09-19 | 4 | -349/+363 | |
| | * | | | | | Revert "Different approach to timing" | Eddie Hung | 2019-09-19 | 4 | -195/+405 | |
| | * | | | | | Different approach to timing | Eddie Hung | 2019-09-19 | 4 | -405/+195 | |
| | * | | | | | Suppress $anyseq warnings | Eddie Hung | 2019-09-19 | 1 | -15/+32 | |
| | * | | | | | Use (* techmap_autopurge *) to suppress techmap warnings | Eddie Hung | 2019-09-19 | 2 | -94/+99 | |
| | * | | | | | D is 25 bits not 24 bits wide | Eddie Hung | 2019-09-19 | 1 | -1/+1 | |
| | * | | | | | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 8 | -90/+502 | |
| | |\ \ \ \ \ | ||||||
| | * | | | | | | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 | Eddie Hung | 2019-09-19 | 1 | -1/+4 | |
| | * | | | | | | Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 | Eddie Hung | 2019-09-19 | 1 | -1/+3 | |
| | * | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-18 | 9 | -948/+19414 | |
| | |\ \ \ \ \ \ | ||||||
| | * | | | | | | | Fix copy-paste | Eddie Hung | 2019-09-18 | 1 | -2/+2 | |
| | * | | | | | | | Mis-spell | Eddie Hung | 2019-09-18 | 1 | -10/+25 | |
| | * | | | | | | | Add pattern detection support for DSP48E1 model, check against vendor | Eddie Hung | 2019-09-18 | 3 | -8/+102 | |
| | * | | | | | | | Add `undef DSP48E1_INST | Eddie Hung | 2019-09-13 | 1 | -4/+5 | |
| | * | | | | | | | Fix D -> P{,COUT} delay | Eddie Hung | 2019-09-13 | 1 | -43/+43 | |
| | * | | | | | | | Add no MULT no DPORT config | Eddie Hung | 2019-09-13 | 4 | -226/+471 | |
| | * | | | | | | | Add support for MULT and DPORT | Eddie Hung | 2019-09-13 | 4 | -10/+588 | |
| | * | | | | | | | Refine diagram | Eddie Hung | 2019-09-13 | 1 | -12/+14 | |
| | * | | | | | | | Add an ASCII drawing | Eddie Hung | 2019-09-12 | 1 | -3/+22 | |
| | * | | | | | | | Finish explanation | Eddie Hung | 2019-09-12 | 2 | -5/+20 | |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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