| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | Move mul2dsp before wreduce | Eddie Hung | 2019-09-20 | 1 | -5/+4 | |
| | * | Tidy up, fix undriven | Eddie Hung | 2019-09-19 | 1 | -32/+34 | |
| | * | $__ABC_REG to have WIDTH parameter | Eddie Hung | 2019-09-19 | 2 | -17/+18 | |
| | * | Fix DSP48E1 timing by breaking P path if MREG or PREG | Eddie Hung | 2019-09-19 | 4 | -349/+363 | |
| | * | Revert "Different approach to timing" | Eddie Hung | 2019-09-19 | 4 | -195/+405 | |
| | * | Different approach to timing | Eddie Hung | 2019-09-19 | 4 | -405/+195 | |
| | * | Suppress $anyseq warnings | Eddie Hung | 2019-09-19 | 1 | -15/+32 | |
| | * | Use (* techmap_autopurge *) to suppress techmap warnings | Eddie Hung | 2019-09-19 | 2 | -94/+99 | |
| | * | D is 25 bits not 24 bits wide | Eddie Hung | 2019-09-19 | 1 | -1/+1 | |
| | * | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp | Eddie Hung | 2019-09-19 | 8 | -90/+502 | |
| | |\ | ||||||
| | * | | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2 | Eddie Hung | 2019-09-19 | 1 | -1/+4 | |
| | * | | Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 | Eddie Hung | 2019-09-19 | 1 | -1/+3 | |
| | * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-18 | 9 | -948/+19414 | |
| | |\ \ | ||||||
| | * | | | Fix copy-paste | Eddie Hung | 2019-09-18 | 1 | -2/+2 | |
| | * | | | Mis-spell | Eddie Hung | 2019-09-18 | 1 | -10/+25 | |
| | * | | | Add pattern detection support for DSP48E1 model, check against vendor | Eddie Hung | 2019-09-18 | 3 | -8/+102 | |
| | * | | | Add `undef DSP48E1_INST | Eddie Hung | 2019-09-13 | 1 | -4/+5 | |
| | * | | | Fix D -> P{,COUT} delay | Eddie Hung | 2019-09-13 | 1 | -43/+43 | |
| | * | | | Add no MULT no DPORT config | Eddie Hung | 2019-09-13 | 4 | -226/+471 | |
| | * | | | Add support for MULT and DPORT | Eddie Hung | 2019-09-13 | 4 | -10/+588 | |
| | * | | | Refine diagram | Eddie Hung | 2019-09-13 | 1 | -12/+14 | |
| | * | | | Add an ASCII drawing | Eddie Hung | 2019-09-12 | 1 | -3/+22 | |
| | * | | | Finish explanation | Eddie Hung | 2019-09-12 | 2 | -5/+20 | |
| | * | | | Rename to techmap_guard | Eddie Hung | 2019-09-12 | 1 | -2/+3 | |
| | * | | | Initial DSP48E1 box support | Eddie Hung | 2019-09-12 | 4 | -0/+867 | |
| | * | | | Set more ports explicitly | Eddie Hung | 2019-09-12 | 1 | -1/+2 | |
| | * | | | Missing space | Eddie Hung | 2019-09-11 | 1 | -0/+1 | |
| | * | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-11 | 5 | -53/+219 | |
| | |\ \ \ | ||||||
| | * | | | | Move "(skip if -nodsp)" message to label | Eddie Hung | 2019-09-10 | 1 | -4/+4 | |
| | * | | | | Be sensitive to signedness | Eddie Hung | 2019-09-10 | 1 | -20/+21 | |
| | * | | | | Really get rid of 'opt_expr -fine' by being explicit | Eddie Hung | 2019-09-10 | 2 | -9/+33 | |
| | * | | | | Remove wreduce call | Eddie Hung | 2019-09-10 | 1 | -1/+0 | |
| | * | | | | Add comment for why opt_expr is necessary | Eddie Hung | 2019-09-10 | 1 | -0/+2 | |
| | * | | | | Revert "Remove "opt_expr -fine" call" | Eddie Hung | 2019-09-10 | 1 | -0/+1 | |
| | * | | | | Rename label to map_dsp | Eddie Hung | 2019-09-10 | 1 | -1/+1 | |
| | * | | | | Remove "opt_expr -fine" call | Eddie Hung | 2019-09-10 | 1 | -1/+0 | |
| | * | | | | Set USE_MULT and USE_SIMD | Eddie Hung | 2019-09-09 | 1 | -1/+3 | |
| | * | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-05 | 20 | -91/+531 | |
| | |\ \ \ \ | ||||||
| | * \ \ \ \ | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-04 | 2 | -7/+8 | |
| | |\ \ \ \ \ | ||||||
| | * \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-30 | 8 | -120/+170 | |
| | |\ \ \ \ \ \ | ||||||
| | * \ \ \ \ \ \ | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 34 | -384/+1864 | |
| | |\ \ \ \ \ \ \ | ||||||
| | | * \ \ \ \ \ \ | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 44 | -564/+1942 | |
| | | |\ \ \ \ \ \ \ | ||||||
| | * | \ \ \ \ \ \ \ | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 14 | -200/+97 | |
| | |\ \ \ \ \ \ \ \ \ | ||||||
| | * \ \ \ \ \ \ \ \ \ | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-15 | 1 | -1/+5 | |
| | |\ \ \ \ \ \ \ \ \ \ | | | |/ / / / / / / / | | |/| | | | | | | | | ||||||
| | | * | | | | | | | | | xilinx: Rework labels for faster Verilator testing | David Shah | 2019-08-13 | 1 | -1/+5 | |
| | * | | | | | | | | | | Only swap ports if $mul and not $__mul | Eddie Hung | 2019-08-13 | 1 | -1/+1 | |
| | * | | | | | | | | | | Add assign PCOUT = P to DSP48E1 | Eddie Hung | 2019-08-13 | 1 | -0/+2 | |
| | * | | | | | | | | | | Add DSP_A_MAXWIDTH_PARTIAL, refactor | Eddie Hung | 2019-08-13 | 2 | -145/+111 | |
| | |/ / / / / / / / / | ||||||
| | * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 6 | -28/+50 | |
| | |\ \ \ \ \ \ \ \ \ | ||||||
| | * | | | | | | | | | | Add wreduce to synth_ice40 -dsp as well | Eddie Hung | 2019-08-09 | 1 | -0/+1 | |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |