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* Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-141-0/+1
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| * Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
* | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
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| * ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| * ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
* | Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
* | synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
* | xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-235-2/+92
* | xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-237-416/+1062
* | xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-229-9/+269
* | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-222-0/+2
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| * | Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-172-0/+2
* | | ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
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* | Makefile: don't assume python is called `python3`Sean Cross2019-10-194-6/+6
* | Merge branch 'master' into mmicko/efinixMiodrag Milanović2019-10-1837-474/+305
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| * ecp5: Add ECLKBRIDGECS blackboxDavid Shah2019-10-111-0/+7
| * ecp5: Add attrmvcp to copy syn_useioff to driving FFDavid Shah2019-10-101-0/+1
| * ecp5: Set syn_useioff on IO FFs to enable packingDavid Shah2019-10-101-8/+8
| * xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-105-33/+14
| * Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0831-228/+236
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| | * Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-044-181/+9
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| | * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0431-227/+235
| * | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
| * | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
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| * | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-2/+6
| * | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
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| * Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-045-31/+4
| * OopsEddie Hung2019-10-041-1/+1
| * Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
* | FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3
* | Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12
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* ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
* ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
* Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
* synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-302-2/+76
* Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2919-31/+3395
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| * Re-orderEddie Hung2019-09-272-2/+2
| * Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
| * Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run onceEddie Hung2019-09-261-9/+4
| * TypoEddie Hung2019-09-261-1/+1
| * select onceEddie Hung2019-09-262-8/+12
| * Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-263-38/+14
| * mul2dsp.v slice namesEddie Hung2019-09-251-5/+5
| * Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicitEddie Hung2019-09-251-3/+1
| * Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"Eddie Hung2019-09-251-2/+6
| * Revert "No need for $__mul anymore?"Eddie Hung2019-09-251-8/+8
| * Only wreduce on t:$addEddie Hung2019-09-251-1/+1
| * Remove _TECHMAP_CELLTYPE_ check since all $mulEddie Hung2019-09-251-6/+2
| * No need for $__mul anymore?Eddie Hung2019-09-251-8/+8
| * Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-251-0/+1
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