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* install *_nowide.lut filesEddie Hung2019-06-292-0/+3
* Remove peepopt call in synth_xilinx since already in synth -run coarseEddie Hung2019-06-281-5/+0
* Update synth_ice40 -device doc to be relevant for -abc9 onlyEddie Hung2019-06-281-2/+2
* Disable boxing of ECP5 dist RAM due to regressionEddie Hung2019-06-281-1/+1
* Add write address to abc_scc_break of ECP5 dist RAMEddie Hung2019-06-281-1/+1
* Fix DO4 typoEddie Hung2019-06-281-1/+1
* Reduce diff with upstreamEddie Hung2019-06-271-4/+2
* Extraneous newlineEddie Hung2019-06-271-1/+0
* Remove noise from ice40/cells_sim.vEddie Hung2019-06-271-5/+0
* Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-273-9/+7
* Remove redundant docEddie Hung2019-06-271-3/+0
* Add warning if synth_xilinx -abc9 with family != xc7Eddie Hung2019-06-271-0/+2
* Merge origin/masterEddie Hung2019-06-274-51/+100
* Add WE to ECP5 dist RAM's abc_scc_break tooEddie Hung2019-06-261-1/+1
* Update comment on boxesEddie Hung2019-06-262-4/+6
* Add "WE" to dist RAM's abc_scc_breakEddie Hung2019-06-261-3/+3
* Remove unused varEddie Hung2019-06-261-1/+1
* Add _nowide variants of LUT libraries in -nowidelut flowsEddie Hung2019-06-264-13/+44
* Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-06-261-2/+10
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| * abc9: Add wire delays to synth_ice40David Shah2019-06-261-2/+10
* | Merge branch 'koriakin/xc7nocarrymux' into xaigEddie Hung2019-06-262-9/+26
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| * synth_ecp5 rename -nomux to -nowidelut, but preserve formerEddie Hung2019-06-261-6/+6
| * Merge branch 'xc7nocarrymux' of https://github.com/koriakin/yosys into koriak...Eddie Hung2019-06-261-4/+24
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| | * synth_xilinx: Add -nocarry and -nomux options.Marcin Kościelnicki2019-04-301-7/+26
* | | Realistic delays for RAM32X1D tooEddie Hung2019-06-251-2/+2
* | | Add RAM32X1D box infoEddie Hung2019-06-252-4/+12
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-255-8/+72
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| * | Add RAM32X1D supportEddie Hung2019-06-245-20/+73
* | | Use LUT delays for dist RAM delaysEddie Hung2019-06-241-4/+4
* | | Re-enable dist RAM boxes for ECP5Eddie Hung2019-06-241-1/+1
* | | Revert "Re-enable dist RAM boxes for ECP5"Eddie Hung2019-06-241-1/+1
* | | Re-enable dist RAM boxes for ECP5Eddie Hung2019-06-241-1/+1
* | | Add Xilinx dist RAM as comb boxesEddie Hung2019-06-242-0/+16
* | | Add comments to ecp5 boxEddie Hung2019-06-221-0/+6
* | | Add comment to xc7 boxEddie Hung2019-06-221-0/+3
* | | Fix and cleanup ice40 boxes for carry in/outEddie Hung2019-06-224-313/+25
* | | Carry in/out box ordering now move to end, not swap with endEddie Hung2019-06-221-12/+12
* | | Remove DFF and RAMD box info for nowEddie Hung2019-06-212-36/+0
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-211-4/+5
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| * | ecp5: Improve mapping of $alu when BI is usedDavid Shah2019-06-211-4/+5
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-201-1/+1
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| * | Fixed small typo in ice40_unlut help summaryacw12512019-06-191-1/+1
| * | Fixed the help summary line for a few commandsacw12512019-06-191-1/+1
* | | Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abcEddie Hung2019-06-201-0/+1
* | | Really permute Xilinx LUT mappings as default LUT6.I5:A6Eddie Hung2019-06-181-16/+16
* | | Revert "Fix (do not) permute LUT inputs, but permute mux selects"Eddie Hung2019-06-181-33/+31
* | | Clean upEddie Hung2019-06-181-6/+4
* | | Fix (do not) permute LUT inputs, but permute mux selectsEddie Hung2019-06-181-31/+33
* | | Fix copy-pasta issueEddie Hung2019-06-171-9/+8
* | | Permute INIT for +/xilinx/lut_map.vEddie Hung2019-06-171-32/+58
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