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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 09:45:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-28 09:45:48 -0700 |
| commit | 0318860b93f7fa4eee148597811c77d67171e5d3 (patch) | |
| tree | 14777ab9eee7778187d97dd956ada710b711d9ac /techlibs | |
| parent | b9ddee0c87ef3f089995d734ad7f5ea1c65eedce (diff) | |
| download | yosys-0318860b93f7fa4eee148597811c77d67171e5d3.tar.gz yosys-0318860b93f7fa4eee148597811c77d67171e5d3.tar.bz2 yosys-0318860b93f7fa4eee148597811c77d67171e5d3.zip | |
Add write address to abc_scc_break of ECP5 dist RAM
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 98f915777..acfb6960e 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -104,7 +104,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z); endmodule // --------------------------------------- -(* abc_box_id=2, abc_scc_break="DI,WRE" *) +(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *) module TRELLIS_DPR16X4 ( input [3:0] DI, input [3:0] WAD, |