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| * | | ecp5: Set syn_useioff on IO FFs to enable packingDavid Shah2019-10-101-8/+8
| * | | xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-105-33/+14
| * | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0831-228/+236
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| | * \ \ Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-044-181/+9
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| | * | | | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0431-227/+235
| * | | | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
| * | | | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
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| * | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-2/+6
| * | | | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
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| * | | Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-045-31/+4
| * | | OopsEddie Hung2019-10-041-1/+1
| * | | Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
* | | | FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3
* | | | Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12
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* | | ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
* | | ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
* | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
* | | synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-302-2/+76
* | | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2919-31/+3395
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| * | | Re-orderEddie Hung2019-09-272-2/+2
| * | | Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
| * | | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run onceEddie Hung2019-09-261-9/+4
| * | | TypoEddie Hung2019-09-261-1/+1
| * | | select onceEddie Hung2019-09-262-8/+12
| * | | Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-263-38/+14
| * | | mul2dsp.v slice namesEddie Hung2019-09-251-5/+5
| * | | Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicitEddie Hung2019-09-251-3/+1
| * | | Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"Eddie Hung2019-09-251-2/+6
| * | | Revert "No need for $__mul anymore?"Eddie Hung2019-09-251-8/+8
| * | | Only wreduce on t:$addEddie Hung2019-09-251-1/+1
| * | | Remove _TECHMAP_CELLTYPE_ check since all $mulEddie Hung2019-09-251-6/+2
| * | | No need for $__mul anymore?Eddie Hung2019-09-251-8/+8
| * | | Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-251-0/+1
| * | | Oops. Actually use __NAME__ in ABC_DSP48E1 macroEddie Hung2019-09-251-1/+1
| * | | Add (* techmap_autopurge *) to abc_unmap.v tooEddie Hung2019-09-231-11/+11
| * | | Add techmap_autopurge to outputs in abc_map.v tooEddie Hung2019-09-231-11/+11
| * | | Revert "Add a xilinx_finalise pass"Eddie Hung2019-09-233-87/+0
| * | | Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"Eddie Hung2019-09-231-38/+38
| * | | Revert "Vivado does not like zero width port connections"Eddie Hung2019-09-231-2/+2
| * | | Vivado does not like zero width port connectionsEddie Hung2019-09-231-2/+2
| * | | Remove (* techmap_autopurge *) from abc_unmap.v since no effectEddie Hung2019-09-231-38/+38
| * | | Add a xilinx_finalise passEddie Hung2019-09-233-0/+87
| * | | GrammarEddie Hung2019-09-201-1/+1
| * | | Fix signedness bugEddie Hung2019-09-201-2/+2
| * | | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-202-3/+2
| * | | Revert "Move mul2dsp before wreduce"Eddie Hung2019-09-201-4/+5
| * | | Move mul2dsp before wreduceEddie Hung2019-09-201-5/+4
| * | | Tidy up, fix undrivenEddie Hung2019-09-191-32/+34
| * | | $__ABC_REG to have WIDTH parameterEddie Hung2019-09-192-17/+18
| * | | Fix DSP48E1 timing by breaking P path if MREG or PREGEddie Hung2019-09-194-349/+363
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