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Age
Files
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*
ecp5: Add support for mapping 36-bit wide PDP BRAMs
David Shah
2019-10-01
6
-1
/
+183
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*
Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}
Eddie Hung
2019-09-30
6
-122
/
+46
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*
synth_xilinx: Support latches, remove used-up FF init values.
Marcin KoĆcielnicki
2019-09-30
2
-2
/
+76
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*
Merge pull request #1359 from YosysHQ/xc7dsp
Eddie Hung
2019-09-29
19
-31
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+3395
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\
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*
Re-order
Eddie Hung
2019-09-27
2
-2
/
+2
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*
Missing (* mul2dsp *) for sliceB
Eddie Hung
2019-09-27
1
-2
/
+2
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*
Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once
Eddie Hung
2019-09-26
1
-9
/
+4
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*
Typo
Eddie Hung
2019-09-26
1
-1
/
+1
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*
select once
Eddie Hung
2019-09-26
2
-8
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+12
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*
Stop trying to be too smart by prematurely optimising
Eddie Hung
2019-09-26
3
-38
/
+14
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*
mul2dsp.v slice names
Eddie Hung
2019-09-25
1
-5
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+5
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*
Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit
Eddie Hung
2019-09-25
1
-3
/
+1
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*
Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"
Eddie Hung
2019-09-25
1
-2
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+6
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*
Revert "No need for $__mul anymore?"
Eddie Hung
2019-09-25
1
-8
/
+8
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*
Only wreduce on t:$add
Eddie Hung
2019-09-25
1
-1
/
+1
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*
Remove _TECHMAP_CELLTYPE_ check since all $mul
Eddie Hung
2019-09-25
1
-6
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+2
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*
No need for $__mul anymore?
Eddie Hung
2019-09-25
1
-8
/
+8
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*
Call 'wreduce' after mul2dsp to avoid unextend()
Eddie Hung
2019-09-25
1
-0
/
+1
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*
Oops. Actually use __NAME__ in ABC_DSP48E1 macro
Eddie Hung
2019-09-25
1
-1
/
+1
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*
Add (* techmap_autopurge *) to abc_unmap.v too
Eddie Hung
2019-09-23
1
-11
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+11
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*
Add techmap_autopurge to outputs in abc_map.v too
Eddie Hung
2019-09-23
1
-11
/
+11
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*
Revert "Add a xilinx_finalise pass"
Eddie Hung
2019-09-23
3
-87
/
+0
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*
Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"
Eddie Hung
2019-09-23
1
-38
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+38
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*
Revert "Vivado does not like zero width port connections"
Eddie Hung
2019-09-23
1
-2
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+2
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*
Vivado does not like zero width port connections
Eddie Hung
2019-09-23
1
-2
/
+2
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*
Remove (* techmap_autopurge *) from abc_unmap.v since no effect
Eddie Hung
2019-09-23
1
-38
/
+38
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*
Add a xilinx_finalise pass
Eddie Hung
2019-09-23
3
-0
/
+87
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*
Grammar
Eddie Hung
2019-09-20
1
-1
/
+1
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*
Fix signedness bug
Eddie Hung
2019-09-20
1
-2
/
+2
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*
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
Eddie Hung
2019-09-20
2
-3
/
+2
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*
Revert "Move mul2dsp before wreduce"
Eddie Hung
2019-09-20
1
-4
/
+5
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*
Move mul2dsp before wreduce
Eddie Hung
2019-09-20
1
-5
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+4
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*
Tidy up, fix undriven
Eddie Hung
2019-09-19
1
-32
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+34
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*
$__ABC_REG to have WIDTH parameter
Eddie Hung
2019-09-19
2
-17
/
+18
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*
Fix DSP48E1 timing by breaking P path if MREG or PREG
Eddie Hung
2019-09-19
4
-349
/
+363
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*
Revert "Different approach to timing"
Eddie Hung
2019-09-19
4
-195
/
+405
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*
Different approach to timing
Eddie Hung
2019-09-19
4
-405
/
+195
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*
Suppress $anyseq warnings
Eddie Hung
2019-09-19
1
-15
/
+32
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*
Use (* techmap_autopurge *) to suppress techmap warnings
Eddie Hung
2019-09-19
2
-94
/
+99
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*
D is 25 bits not 24 bits wide
Eddie Hung
2019-09-19
1
-1
/
+1
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*
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
Eddie Hung
2019-09-19
8
-90
/
+502
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\
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*
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synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2
Eddie Hung
2019-09-19
1
-1
/
+4
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*
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Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2
Eddie Hung
2019-09-19
1
-1
/
+3
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*
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Merge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung
2019-09-18
9
-948
/
+19414
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\
\
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*
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Fix copy-paste
Eddie Hung
2019-09-18
1
-2
/
+2
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*
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Mis-spell
Eddie Hung
2019-09-18
1
-10
/
+25
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*
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Add pattern detection support for DSP48E1 model, check against vendor
Eddie Hung
2019-09-18
3
-8
/
+102
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*
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Add `undef DSP48E1_INST
Eddie Hung
2019-09-13
1
-4
/
+5
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*
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Fix D -> P{,COUT} delay
Eddie Hung
2019-09-13
1
-43
/
+43
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*
|
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Add no MULT no DPORT config
Eddie Hung
2019-09-13
4
-226
/
+471
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