iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge branch 'master' into xaig	Eddie Hung	2019-02-19	2	-86/+43
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* \|	synth_ice40 to have new -abc9 arg	Eddie Hung	2019-02-14	1	-4/+12
* \|	Cope WIDTH of ff/latch cells is default of zero	Eddie Hung	2019-02-06	1	-6/+6
* \|	Add INIT parameter to all ff/latch cells	Eddie Hung	2019-02-06	2	-43/+86
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*	Fixed Anlogic simulation model	Miodrag Milanovic	2019-01-25	1	-1/+1
*	Add SF2 IO buffer insertion	Clifford Wolf	2019-01-17	4	-1/+168
*	Add "synth_sf2 -vlog", fix "synth_sf2 -edif"	Clifford Wolf	2019-01-17	1	-2/+17
*	Merge pull request #777 from mmicko/achronix_cell_sim_fix	Clifford Wolf	2019-01-04	1	-1/+1
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\| *	Fix cells_sim.v for Achronix FPGA	Miodrag Milanovic	2019-01-04	1	-1/+1
* \|	Unify usage of noflatten among architectures	Miodrag Milanovic	2019-01-04	4	-8/+16
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*	Merge pull request #755 from Icenowy/anlogic-dram-init	Clifford Wolf	2019-01-02	6	-2/+96
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\| *	anlogic: implement DRAM initialization	Icenowy Zheng	2018-12-20	6	-2/+96
* \|	Merge pull request #750 from Icenowy/anlogic-ff-init	Clifford Wolf	2019-01-02	2	-14/+15
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\| * \|	anlogic: set the init value of DFFs	Icenowy Zheng	2018-12-18	2	-14/+15
* \| \|	Merge pull request #772 from whitequark/synth_lut	Clifford Wolf	2019-01-02	2	-7/+41
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\| * \| \|	synth_ice40: use 4-LUT coarse synthesis mode.	whitequark	2019-01-02	1	-1/+1
\| * \| \|	synth: add k-LUT mode.	whitequark	2019-01-02	1	-2/+36
\| * \| \|	synth: improve script documentation. NFC.	whitequark	2019-01-02	1	-6/+6
* \| \| \|	Merge pull request #771 from whitequark/techmap_cmp2lut	Clifford Wolf	2019-01-02	2	-1/+106
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\| * \| \|	cmp2lut: new techmap pass.	whitequark	2019-01-02	2	-1/+106
* \| \| \|	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	15	-22/+22
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* \| \|	Merge pull request #766 from Icenowy/anlogic-latches	Clifford Wolf	2018-12-31	1	-0/+12
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\| * \| \|	anlogic: add latch cells	Icenowy Zheng	2018-12-25	1	-0/+12
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* / \|	Fix 7 instances of add_share_file to add_gen_share_file	Larry Doolittle	2018-12-29	1	-8/+8
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* \|	Merge pull request #752 from Icenowy/anlogic-lut-cost	Clifford Wolf	2018-12-19	1	-1/+1
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\| * \|	Anlogic: let LUT5/6 have more cost than LUT4-	Icenowy Zheng	2018-12-19	1	-1/+1
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* \|	Merge pull request #753 from Icenowy/anlogic-makefile-fix	Clifford Wolf	2018-12-19	1	-0/+1
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\| * \|	anlogic: fix Makefile.inc	Icenowy Zheng	2018-12-19	1	-0/+1
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* /	anlogic: fix dbits of Anlogic Eagle DRAM16X4	Icenowy Zheng	2018-12-18	1	-1/+1
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*	anlogic: add support for Eagle Distributed RAM	Icenowy Zheng	2018-12-17	4	-1/+43
*	Revert "Leave only real black box cells"	Icenowy Zheng	2018-12-17	1	-0/+312
*	Rename "fine:" label to "map:" in "synth_ice40"	Clifford Wolf	2018-12-16	1	-1/+1
*	Merge pull request #724 from whitequark/equiv_opt	Clifford Wolf	2018-12-16	1	-0/+2
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\| *	equiv_opt: pass -D EQUIV when techmapping.	whitequark	2018-12-07	1	-0/+2
* \|	Merge pull request #730 from smunaut/ffssr_dont_touch	Clifford Wolf	2018-12-16	1	-0/+3
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\| * \|	ice40: Honor the "dont_touch" attribute in FFSSR pass	Sylvain Munaut	2018-12-08	1	-0/+3
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* \|	Merge pull request #725 from olofk/ram4k-init	Clifford Wolf	2018-12-16	1	-0/+19
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\| * \|	Only use non-blocking assignments of SB_RAM40_4K for yosys	Olof Kindgren	2018-12-06	1	-0/+19
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* /	synth_ice40: split `map_gates` off `fine`.	whitequark	2018-12-06	1	-0/+4
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*	synth_ice40: add -noabc option, to use built-in LUT techmapping.	whitequark	2018-12-05	1	-2/+16
*	gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.	whitequark	2018-12-05	2	-0/+88
*	Fix typo.	whitequark	2018-12-05	1	-2/+2
*	Merge pull request #713 from Diego-HR/master	Clifford Wolf	2018-12-05	5	-12/+91
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\| *	Changes in GoWin synth commands and ALU primitive support	Diego H	2018-12-03	5	-12/+91
* \|	Merge pull request #712 from mmicko/anlogic-support	Clifford Wolf	2018-12-05	7	-0/+1278
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\| * \|	Leave only real black box cells	Miodrag Milanovic	2018-12-02	1	-312/+0
\| * \|	Initial support for Anlogic FPGA	Miodrag Milanovic	2018-12-01	7	-0/+1590
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* \|	opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.	whitequark	2018-12-05	1	-2/+2
* \|	synth_ice40: add -relut option, to run ice40_unlut and opt_lut.	whitequark	2018-12-05	1	-1/+13
* \|	Extract ice40_unlut pass from ice40_opt.	whitequark	2018-12-05	3	-13/+109