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Author
Age
Files
Lines
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Add INIT parameter to all ff/latch cells
Eddie Hung
2019-02-06
2
-43
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+86
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Fixed Anlogic simulation model
Miodrag Milanovic
2019-01-25
1
-1
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+1
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Add SF2 IO buffer insertion
Clifford Wolf
2019-01-17
4
-1
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+168
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Add "synth_sf2 -vlog", fix "synth_sf2 -edif"
Clifford Wolf
2019-01-17
1
-2
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+17
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Merge pull request #777 from mmicko/achronix_cell_sim_fix
Clifford Wolf
2019-01-04
1
-1
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+1
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Fix cells_sim.v for Achronix FPGA
Miodrag Milanovic
2019-01-04
1
-1
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+1
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Unify usage of noflatten among architectures
Miodrag Milanovic
2019-01-04
4
-8
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+16
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Merge pull request #755 from Icenowy/anlogic-dram-init
Clifford Wolf
2019-01-02
6
-2
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+96
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anlogic: implement DRAM initialization
Icenowy Zheng
2018-12-20
6
-2
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+96
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Merge pull request #750 from Icenowy/anlogic-ff-init
Clifford Wolf
2019-01-02
2
-14
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+15
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anlogic: set the init value of DFFs
Icenowy Zheng
2018-12-18
2
-14
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+15
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Merge pull request #772 from whitequark/synth_lut
Clifford Wolf
2019-01-02
2
-7
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+41
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synth_ice40: use 4-LUT coarse synthesis mode.
whitequark
2019-01-02
1
-1
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+1
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synth: add k-LUT mode.
whitequark
2019-01-02
1
-2
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+36
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synth: improve script documentation. NFC.
whitequark
2019-01-02
1
-6
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+6
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Merge pull request #771 from whitequark/techmap_cmp2lut
Clifford Wolf
2019-01-02
2
-1
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+106
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cmp2lut: new techmap pass.
whitequark
2019-01-02
2
-1
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+106
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Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
15
-22
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+22
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Merge pull request #766 from Icenowy/anlogic-latches
Clifford Wolf
2018-12-31
1
-0
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+12
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anlogic: add latch cells
Icenowy Zheng
2018-12-25
1
-0
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+12
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Fix 7 instances of add_share_file to add_gen_share_file
Larry Doolittle
2018-12-29
1
-8
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+8
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Merge pull request #752 from Icenowy/anlogic-lut-cost
Clifford Wolf
2018-12-19
1
-1
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+1
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Anlogic: let LUT5/6 have more cost than LUT4-
Icenowy Zheng
2018-12-19
1
-1
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+1
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Merge pull request #753 from Icenowy/anlogic-makefile-fix
Clifford Wolf
2018-12-19
1
-0
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+1
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anlogic: fix Makefile.inc
Icenowy Zheng
2018-12-19
1
-0
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+1
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anlogic: fix dbits of Anlogic Eagle DRAM16X4
Icenowy Zheng
2018-12-18
1
-1
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+1
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anlogic: add support for Eagle Distributed RAM
Icenowy Zheng
2018-12-17
4
-1
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+43
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Revert "Leave only real black box cells"
Icenowy Zheng
2018-12-17
1
-0
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+312
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Rename "fine:" label to "map:" in "synth_ice40"
Clifford Wolf
2018-12-16
1
-1
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+1
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Merge pull request #724 from whitequark/equiv_opt
Clifford Wolf
2018-12-16
1
-0
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+2
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equiv_opt: pass -D EQUIV when techmapping.
whitequark
2018-12-07
1
-0
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+2
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Merge pull request #730 from smunaut/ffssr_dont_touch
Clifford Wolf
2018-12-16
1
-0
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+3
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ice40: Honor the "dont_touch" attribute in FFSSR pass
Sylvain Munaut
2018-12-08
1
-0
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+3
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Merge pull request #725 from olofk/ram4k-init
Clifford Wolf
2018-12-16
1
-0
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+19
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Only use non-blocking assignments of SB_RAM40_4K for yosys
Olof Kindgren
2018-12-06
1
-0
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+19
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synth_ice40: split `map_gates` off `fine`.
whitequark
2018-12-06
1
-0
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+4
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synth_ice40: add -noabc option, to use built-in LUT techmapping.
whitequark
2018-12-05
1
-2
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+16
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gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
whitequark
2018-12-05
2
-0
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+88
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Fix typo.
whitequark
2018-12-05
1
-2
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+2
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Merge pull request #713 from Diego-HR/master
Clifford Wolf
2018-12-05
5
-12
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+91
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Changes in GoWin synth commands and ALU primitive support
Diego H
2018-12-03
5
-12
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+91
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Merge pull request #712 from mmicko/anlogic-support
Clifford Wolf
2018-12-05
7
-0
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+1278
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Leave only real black box cells
Miodrag Milanovic
2018-12-02
1
-312
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+0
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Initial support for Anlogic FPGA
Miodrag Milanovic
2018-12-01
7
-0
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+1590
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opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
whitequark
2018-12-05
1
-2
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+2
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synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
whitequark
2018-12-05
1
-1
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+13
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Extract ice40_unlut pass from ice40_opt.
whitequark
2018-12-05
3
-13
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+109
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ice40: Add option to only use CE if it'd be use by more than X FFs
Sylvain Munaut
2018-11-27
1
-0
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+14
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Merge pull request #697 from eddiehung/xilinx_ps7
Clifford Wolf
2018-11-12
2
-0
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+624
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Add support for Xilinx PS7 block
Eddie Hung
2018-11-10
2
-0
/
+624
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