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* Add INIT parameter to all ff/latch cellsEddie Hung2019-02-062-43/+86
* Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
* Add SF2 IO buffer insertionClifford Wolf2019-01-174-1/+168
* Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
* Merge pull request #777 from mmicko/achronix_cell_sim_fixClifford Wolf2019-01-041-1/+1
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| * Fix cells_sim.v for Achronix FPGAMiodrag Milanovic2019-01-041-1/+1
* | Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-044-8/+16
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* Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
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| * anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
* | Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-022-14/+15
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| * | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
* | | Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-022-7/+41
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| * | | synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
| * | | synth: add k-LUT mode.whitequark2019-01-021-2/+36
| * | | synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
* | | | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-022-1/+106
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| * | | cmp2lut: new techmap pass.whitequark2019-01-022-1/+106
* | | | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-0215-22/+22
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* | | Merge pull request #766 from Icenowy/anlogic-latchesClifford Wolf2018-12-311-0/+12
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| * | | anlogic: add latch cellsIcenowy Zheng2018-12-251-0/+12
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* / | Fix 7 instances of add_share_file to add_gen_share_fileLarry Doolittle2018-12-291-8/+8
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* | Merge pull request #752 from Icenowy/anlogic-lut-costClifford Wolf2018-12-191-1/+1
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| * | Anlogic: let LUT5/6 have more cost than LUT4-Icenowy Zheng2018-12-191-1/+1
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* | Merge pull request #753 from Icenowy/anlogic-makefile-fixClifford Wolf2018-12-191-0/+1
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| * | anlogic: fix Makefile.incIcenowy Zheng2018-12-191-0/+1
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* / anlogic: fix dbits of Anlogic Eagle DRAM16X4Icenowy Zheng2018-12-181-1/+1
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* anlogic: add support for Eagle Distributed RAMIcenowy Zheng2018-12-174-1/+43
* Revert "Leave only real black box cells"Icenowy Zheng2018-12-171-0/+312
* Rename "fine:" label to "map:" in "synth_ice40"Clifford Wolf2018-12-161-1/+1
* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-161-0/+2
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| * equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-071-0/+2
* | Merge pull request #730 from smunaut/ffssr_dont_touchClifford Wolf2018-12-161-0/+3
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| * | ice40: Honor the "dont_touch" attribute in FFSSR passSylvain Munaut2018-12-081-0/+3
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* | Merge pull request #725 from olofk/ram4k-initClifford Wolf2018-12-161-0/+19
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| * | Only use non-blocking assignments of SB_RAM40_4K for yosysOlof Kindgren2018-12-061-0/+19
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* / synth_ice40: split `map_gates` off `fine`.whitequark2018-12-061-0/+4
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* synth_ice40: add -noabc option, to use built-in LUT techmapping.whitequark2018-12-051-2/+16
* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-052-0/+88
* Fix typo.whitequark2018-12-051-2/+2
* Merge pull request #713 from Diego-HR/masterClifford Wolf2018-12-055-12/+91
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| * Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-035-12/+91
* | Merge pull request #712 from mmicko/anlogic-supportClifford Wolf2018-12-057-0/+1278
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| * | Leave only real black box cellsMiodrag Milanovic2018-12-021-312/+0
| * | Initial support for Anlogic FPGAMiodrag Milanovic2018-12-017-0/+1590
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* | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-2/+2
* | synth_ice40: add -relut option, to run ice40_unlut and opt_lut.whitequark2018-12-051-1/+13
* | Extract ice40_unlut pass from ice40_opt.whitequark2018-12-053-13/+109
* | ice40: Add option to only use CE if it'd be use by more than X FFsSylvain Munaut2018-11-271-0/+14
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* Merge pull request #697 from eddiehung/xilinx_ps7Clifford Wolf2018-11-122-0/+624
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| * Add support for Xilinx PS7 blockEddie Hung2018-11-102-0/+624
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