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| * | | Realistic delays for RAM32X1D tooEddie Hung2019-06-251-2/+2
| * | | Add RAM32X1D box infoEddie Hung2019-06-252-4/+12
| * | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-255-8/+72
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* | | | This optimisation doesn't seem to work...Eddie Hung2019-06-251-24/+24
* | | | Realistic delays for RAM32X1D tooEddie Hung2019-06-241-2/+2
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-241-4/+4
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| * | | Use LUT delays for dist RAM delaysEddie Hung2019-06-241-4/+4
* | | | Add RAM32X1D box infoEddie Hung2019-06-242-4/+12
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-243-1/+17
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| * | | Re-enable dist RAM boxes for ECP5Eddie Hung2019-06-241-1/+1
| * | | Revert "Re-enable dist RAM boxes for ECP5"Eddie Hung2019-06-241-1/+1
| * | | Re-enable dist RAM boxes for ECP5Eddie Hung2019-06-241-1/+1
| * | | Add Xilinx dist RAM as comb boxesEddie Hung2019-06-242-0/+16
* | | | Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7muxEddie Hung2019-06-245-8/+72
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| * | | Add RAM32X1D supportEddie Hung2019-06-245-20/+73
* | | | Reduce MuxFx resources in mux techmappingEddie Hung2019-06-241-10/+30
* | | | Reduce number of decomposed muxes during techmapEddie Hung2019-06-241-14/+11
* | | | Revert "Fix techmapping muxes some more"Eddie Hung2019-06-241-4/+4
* | | | Move commentEddie Hung2019-06-241-3/+3
* | | | Fix techmapping muxes some moreEddie Hung2019-06-241-4/+4
* | | | Fix mux techmappingEddie Hung2019-06-241-19/+20
* | | | Modify costs for muxcoverEddie Hung2019-06-241-1/+15
* | | | Change synth_xilinx's -nomux to -minmuxf <int>Eddie Hung2019-06-243-54/+82
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-227-361/+46
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| * | | Add comments to ecp5 boxEddie Hung2019-06-221-0/+6
| * | | Add comment to xc7 boxEddie Hung2019-06-221-0/+3
| * | | Fix and cleanup ice40 boxes for carry in/outEddie Hung2019-06-224-313/+25
| * | | Carry in/out box ordering now move to end, not swap with endEddie Hung2019-06-221-12/+12
| * | | Remove DFF and RAMD box info for nowEddie Hung2019-06-212-36/+0
* | | | Remove $_MUX4_ techmap ruleEddie Hung2019-06-211-11/+0
* | | | Fix wreduce call (!!!), tweak muxcover costsEddie Hung2019-06-211-5/+6
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-211-4/+5
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| * | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-211-4/+5
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| | * | ecp5: Improve mapping of $alu when BI is usedDavid Shah2019-06-211-4/+5
| * | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-201-1/+1
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| * | | Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abcEddie Hung2019-06-201-0/+1
* | | | Constrain wreduce only if wide muxEddie Hung2019-06-211-1/+4
* | | | Simplify and comment out mux_map.vEddie Hung2019-06-211-6/+11
* | | | synth_xilinx to now wreduce except $mux, remove extra peepoptEddie Hung2019-06-211-8/+1
* | | | mux_map to no longer copy last value into 1'bxEddie Hung2019-06-211-19/+2
* | | | Fix spacingEddie Hung2019-06-211-3/+3
* | | | Fix spacing again, A_forward -> A_backwardEddie Hung2019-06-211-38/+40
* | | | Restore wreduce to synth_xilinx, after muxcoverEddie Hung2019-06-211-0/+1
* | | | Revert B_SIGNED optimisation, since only works for Y_WIDTH==1Eddie Hung2019-06-211-4/+3
* | | | Fix spacingEddie Hung2019-06-211-15/+15
* | | | synth_xilinx to use _ABC macro, and perform muxpack againEddie Hung2019-06-211-5/+5
* | | | Add $__XILINX_MUXF78 to preserve entire boxEddie Hung2019-06-213-7/+28
* | | | Fix alignmentEddie Hung2019-06-211-1/+1
* | | | Add FIXME about need for -mux4Eddie Hung2019-06-211-0/+2
* | | | Since muxcover uses MUX4s, blast them back to gates hereEddie Hung2019-06-211-0/+7
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