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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 23:05:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 23:05:28 -0700 |
| commit | 158325956e6bf711137e6198fb88e95a1e6250b9 (patch) | |
| tree | 274d38a57805df66a212a023df717304e0d125d0 /techlibs | |
| parent | 3825068a75b2d7ccb0953c92040474f95274b76a (diff) | |
| download | yosys-158325956e6bf711137e6198fb88e95a1e6250b9.tar.gz yosys-158325956e6bf711137e6198fb88e95a1e6250b9.tar.bz2 yosys-158325956e6bf711137e6198fb88e95a1e6250b9.zip | |
Realistic delays for RAM32X1D too
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index c95ba4969..67d1ffb1e 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -39,8 +39,8 @@ CARRY4 3 1 10 8 # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE # Outputs: DPO SPO RAM32X1D 4 0 13 2 -- - - - - - 124 124 124 124 124 - - -124 124 124 124 124 - - - - - - - - +- - - - - - 631 472 407 238 127 - - +631 472 407 238 127 - - - - - - - - # SLICEM/A6LUT # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE |