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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 11:13:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 11:13:01 -0700 |
| commit | c6b4653ebe83fc5bacaeb92fe7c63a8d52bd523e (patch) | |
| tree | 11e887ccdeb0bba07ee7c7014d4380a6005fff09 /techlibs | |
| parent | dd22edcd28f2ef9411dde9a941f1fefe05d7bff1 (diff) | |
| download | yosys-c6b4653ebe83fc5bacaeb92fe7c63a8d52bd523e.tar.gz yosys-c6b4653ebe83fc5bacaeb92fe7c63a8d52bd523e.tar.bz2 yosys-c6b4653ebe83fc5bacaeb92fe7c63a8d52bd523e.zip | |
Since muxcover uses MUX4s, blast them back to gates here
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/mux_map.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v index 6ad83a488..b7ff6ca90 100644 --- a/techlibs/xilinx/mux_map.v +++ b/techlibs/xilinx/mux_map.v @@ -84,3 +84,10 @@ module \$shiftx (A, B, Y); end endgenerate endmodule + +module \$_MUX4_ (A, B, C, D, S, T, Y); +input A, B, C, D, S, T; +output Y; +assign Y = T ? (S ? D : C) : + (S ? B : A); +endmodule |