| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added map, par and bitgen to xlinx7 example | Clifford Wolf | 2013-10-16 | 1 | -2/+39 |
| * | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 | 6 | -7/+7 |
| * | Added spice testbench to techlibs/cmos | Clifford Wolf | 2013-09-14 | 4 | -3/+73 |
| * | Added spice backend | Clifford Wolf | 2013-09-14 | 4 | -0/+78 |
| * | Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos) | Clifford Wolf | 2013-08-27 | 1 | -2/+10 |
| * | Added simple xilinx7 technology mapping files | Clifford Wolf | 2013-08-22 | 4 | -0/+167 |
| * | Implemented same div-by-zero behavior as found in other synthesis tools | Clifford Wolf | 2013-08-15 | 1 | -2/+31 |
| * | Added $div and $mod technology mapping | Clifford Wolf | 2013-08-09 | 1 | -9/+93 |
| * | Added $lut cells and abc lut mapping support | Clifford Wolf | 2013-07-23 | 1 | -0/+32 |
| * | Fixed shift ops with large right hand side | Clifford Wolf | 2013-07-09 | 1 | -6/+6 |
| * | More fixes for bugs found using xsthammer | Clifford Wolf | 2013-06-13 | 1 | -8/+7 |
| * | More sign-extension related fixes | Clifford Wolf | 2013-06-10 | 1 | -12/+13 |
| * | Implemented technology mapping for multipliers (using array multiplier) | Clifford Wolf | 2013-06-03 | 1 | -4/+30 |
| * | Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v | Clifford Wolf | 2013-04-07 | 1 | -4/+4 |
| * | Added EXTRA_TARGETS Makefile variable | Clifford Wolf | 2013-03-28 | 1 | -1/+1 |
| * | Tiny bugfix in simlib.v | Clifford Wolf | 2013-03-26 | 1 | -1/+0 |
| * | Fixed stdcells.v for $adff with undef reset value | Clifford Wolf | 2013-03-24 | 1 | -63/+68 |
| * | More support code for $sr cells | Clifford Wolf | 2013-03-14 | 1 | -0/+21 |
| * | added .gitignore files | Clifford Wolf | 2013-01-05 | 1 | -0/+1 |
| * | initial import | Clifford Wolf | 2013-01-05 | 5 | -0/+2447 |
