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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-26 19:06:28 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-26 19:06:28 +0100 |
| commit | 26f2439551697c0511bd0c5375ce69e26973d4ca (patch) | |
| tree | 1078e11811f85b6389995d2dc5345e970d5f6ff4 /techlibs | |
| parent | 7a99349de4d9375845c05e3ac17d1eed366aab2e (diff) | |
| download | yosys-26f2439551697c0511bd0c5375ce69e26973d4ca.tar.gz yosys-26f2439551697c0511bd0c5375ce69e26973d4ca.tar.bz2 yosys-26f2439551697c0511bd0c5375ce69e26973d4ca.zip | |
Tiny bugfix in simlib.v
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/simlib.v | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/simlib.v b/techlibs/simlib.v index 29c13503b..8675a4d0f 100644 --- a/techlibs/simlib.v +++ b/techlibs/simlib.v @@ -646,7 +646,6 @@ module \$sr (S, R, Q); parameter WIDTH = 0; -input CLK; input [WIDTH-1:0] S, R; output reg [WIDTH-1:0] Q; |