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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-09 18:59:59 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-09 18:59:59 +0200 |
| commit | 7daeee340a7edad3f4450e1392f8bad8d8b9cb7c (patch) | |
| tree | 42106533b2f4b23bfcc594a2ac73301895faf182 /techlibs | |
| parent | e8da3ea7b647f2c1eeba8a84590df7b05ca4e046 (diff) | |
| download | yosys-7daeee340a7edad3f4450e1392f8bad8d8b9cb7c.tar.gz yosys-7daeee340a7edad3f4450e1392f8bad8d8b9cb7c.tar.bz2 yosys-7daeee340a7edad3f4450e1392f8bad8d8b9cb7c.zip | |
Fixed shift ops with large right hand side
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/stdcells.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/techlibs/stdcells.v b/techlibs/stdcells.v index 59209f9bc..304280bf6 100644 --- a/techlibs/stdcells.v +++ b/techlibs/stdcells.v @@ -446,7 +446,7 @@ generate assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; \$shift #( .WIDTH(WIDTH), - .SHIFT(0 - (2 ** i)) + .SHIFT(0 - (2 ** (i > 30 ? 30 : i))) ) sh ( .X(0), .A(unshifted), @@ -499,7 +499,7 @@ generate assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; \$shift #( .WIDTH(WIDTH), - .SHIFT(2 ** i) + .SHIFT(2 ** (i > 30 ? 30 : i)) ) sh ( .X(0), .A(unshifted), @@ -552,7 +552,7 @@ generate assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; \$shift #( .WIDTH(WIDTH), - .SHIFT(0 - (2 ** i)) + .SHIFT(0 - (2 ** (i > 30 ? 30 : i))) ) sh ( .X(0), .A(unshifted), @@ -614,7 +614,7 @@ generate assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; \$shift #( .WIDTH(WIDTH), - .SHIFT(2 ** i) + .SHIFT(2 ** (i > 30 ? 30 : i)) ) sh ( .X(A_SIGNED && A[A_WIDTH-1]), .A(unshifted), @@ -800,7 +800,7 @@ input [B_WIDTH-1:0] B; output Y; wire carry, carry_sign; -wire [WIDTH-1:0] A_buf, B_buf, Y_buf; +wire [WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); @@ -825,7 +825,7 @@ input [B_WIDTH-1:0] B; output Y; wire carry, carry_sign; -wire [WIDTH-1:0] A_buf, B_buf, Y_buf; +wire [WIDTH-1:0] A_buf, B_buf; \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); |