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Author
Age
Files
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...
*
|
Add flooring modulo operator
Xiretza
2020-05-28
2
-3
/
+124
*
|
xilinx: tidy up cells_sim.v a little
Eddie Hung
2020-05-25
1
-5
/
+7
|
/
*
ecp5: cleanup unused +/ecp5/abc9_model.v
Eddie Hung
2020-05-23
3
-14
/
+0
*
Add force_downto and force_upto wire attributes.
Marcelina Kościelnicka
2020-05-19
39
-24
/
+232
*
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
Eddie Hung
2020-05-14
2
-14
/
+2
*
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
Eddie Hung
2020-05-14
2
-5
/
+4
*
abc9_ops/xaiger: further reducing Module::derive() calls by ...
Eddie Hung
2020-05-14
2
-7
/
+5
*
Cleanup; reduce Module::derive() calls
Eddie Hung
2020-05-14
2
-4
/
+4
*
ecp5: latches_map.v if *not* -asyncprld
Eddie Hung
2020-05-14
1
-2
/
+2
*
ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v
Eddie Hung
2020-05-14
4
-43
/
+3
*
ecp5: fix rebase mistake
Eddie Hung
2020-05-14
1
-3
/
+3
*
xilinx: gate specify/attributes from iverilog
Eddie Hung
2020-05-14
1
-1
/
+3
*
abc9: only do +/abc9_map if `DFF
Eddie Hung
2020-05-14
1
-0
/
+2
*
ecp5: TRELLIS_FF bypass path only in async mode
Eddie Hung
2020-05-14
1
-8
/
+8
*
xilinx/ice40/ecp5: zinit requires selected wires, so select them all
Eddie Hung
2020-05-14
3
-4
/
+4
*
xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells
Eddie Hung
2020-05-14
3
-4
/
+198
*
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
Eddie Hung
2020-05-14
8
-763
/
+129
*
abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
Eddie Hung
2020-05-14
2
-10
/
+26
*
synth_*: no need to explicitly read +/abc9_model.v
Eddie Hung
2020-05-14
4
-4
/
+3
*
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
Eddie Hung
2020-05-14
4
-0
/
+55
*
abc9_ops: -prep_dff_map to error if async flop found
Eddie Hung
2020-05-14
1
-4
/
+0
*
Uncomment negative setup times; clamp to zero for connectivity
Eddie Hung
2020-05-14
1
-13
/
+29
*
Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"
Eddie Hung
2020-05-14
3
-220
/
+64
*
ecp5: (* abc9_flop *) gated behind YOSYS
Eddie Hung
2020-05-14
1
-0
/
+2
*
ecp5: add synth_ecp5 -dff to work with -abc9
Eddie Hung
2020-05-14
2
-12
/
+47
*
ice40: synth_ice40 cleanup
Eddie Hung
2020-05-14
1
-13
/
+3
*
ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init
Eddie Hung
2020-05-14
3
-64
/
+220
*
ice40: add synth_ice40 -dff option, support with -abc9
Eddie Hung
2020-05-14
2
-8
/
+41
*
ice40: split out cells_map.v into ff_map.v
Eddie Hung
2020-05-14
3
-31
/
+29
*
synth_xilinx: rename dff_mode -> dff
Eddie Hung
2020-05-14
1
-8
/
+10
*
abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes
Eddie Hung
2020-05-14
5
-369
/
+5
*
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
Claire Wolf
2020-05-14
2
-7
/
+30
|
\
|
*
techlibs/common: more robustness when *_WIDTH = 0
Eddie Hung
2020-05-05
2
-7
/
+30
*
|
ice40: fix ICESTORM_LC process sensitivity
Eddie Hung
2020-05-12
1
-1
/
+1
*
|
ice40: fix whitespace
Eddie Hung
2020-05-12
1
-15
/
+14
*
|
ecp5: Add missing SERDES parameters
David Shah
2020-05-12
1
-0
/
+4
*
|
intel_alm: direct LUTRAM cell instantiation
Dan Ravensloft
2020-05-07
8
-52
/
+143
*
|
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
Eddie Hung
2020-05-04
3
-11
/
+34
|
/
*
gowin,ecp5: remove generated files in `make clean`.
whitequark
2020-04-24
2
-2
/
+10
*
intel_alm: cleanup duplication
Dan Ravensloft
2020-04-24
5
-113
/
+64
*
intel_alm: work around a Quartus ICE
Dan Ravensloft
2020-04-23
1
-0
/
+10
*
ecp5: ecp5_gsr to skip cells that don't have GSR parameter again
Eddie Hung
2020-04-22
1
-1
/
+1
*
xilinx: improve xilinx_dffopt message
Eddie Hung
2020-04-22
1
-3
/
+6
*
Cleanup use of hard-coded default parameters in light of #1945
Eddie Hung
2020-04-22
2
-12
/
+6
*
intel_alm: Documentation improvements
Dan Ravensloft
2020-04-21
3
-14
/
+127
*
Use default parameter value in getParam
Marcelina Kościelnicka
2020-04-21
1
-3
/
+3
*
ecp5: Force SIGNED ports to be 1 bit
David Shah
2020-04-16
1
-1
/
+1
*
Fix the truth table for $_SR_* cells.
Marcelina Kościelnicka
2020-04-15
3
-26
/
+21
*
Get rid of dffsr2dff.
Marcelina Kościelnicka
2020-04-15
9
-10
/
+1
*
synth_intel_alm: VQM support
Dan Ravensloft
2020-04-15
2
-6
/
+3
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