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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 13:59:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 16:25:23 -0700 |
| commit | d2d90e4504a0fb43c35584484e0b949be7225b2b (patch) | |
| tree | 7e79f118d34492d8bd1704a17ffdf946e1f9557e /techlibs | |
| parent | f582eb14af21450129e9cefbcaa5e7e3ad2e7783 (diff) | |
| download | yosys-d2d90e4504a0fb43c35584484e0b949be7225b2b.tar.gz yosys-d2d90e4504a0fb43c35584484e0b949be7225b2b.tar.bz2 yosys-d2d90e4504a0fb43c35584484e0b949be7225b2b.zip | |
xilinx: improve xilinx_dffopt message
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/xilinx_dffopt.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index c608db883..c9d63c9f7 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -292,18 +292,21 @@ unmap: LutData final_lut; if (worthy_post_r) { final_lut = lut_d_post_r; - log(" Merging R LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); } else if (worthy_post_s) { final_lut = lut_d_post_s; - log(" Merging S LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); } else if (worthy_post_ce) { final_lut = lut_d_post_ce; - log(" Merging CE LUT for %s/%s (%d -> %d)\n", log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); } else { // Nothing to do here. continue; } + std::string ports; + if (worthy_post_r) ports += " + R"; + if (worthy_post_s) ports += " + S"; + if (worthy_post_ce) ports += " + CE"; + log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second)); + // Okay, we're doing it. Unmap ports. if (worthy_post_r) { cell->unsetParam(ID(IS_R_INVERTED)); |