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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-21 20:44:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:57 -0700 |
| commit | ca4f8c94441c16392ffc02a6117f9b3883e7042e (patch) | |
| tree | b7af1fa8e8c132f47683ad089690e7d92540e951 /techlibs | |
| parent | 57c478c537ef23c05ca34ecdf4c4334fd82c104e (diff) | |
| download | yosys-ca4f8c94441c16392ffc02a6117f9b3883e7042e.tar.gz yosys-ca4f8c94441c16392ffc02a6117f9b3883e7042e.tar.bz2 yosys-ca4f8c94441c16392ffc02a6117f9b3883e7042e.zip | |
xilinx: gate specify/attributes from iverilog
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index cd611399e..d87cfe91b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -1678,7 +1678,6 @@ module RAM128X1D ( // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981 if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */; if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; -`endif (A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; (A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; (A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */; @@ -1693,6 +1692,7 @@ module RAM128X1D ( (DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; (DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */; (DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */; +`endif endspecify endmodule @@ -3036,8 +3036,10 @@ endmodule // Virtex 6, Series 7. +`ifdef YOSYS (* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG), lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) *) +`endif module DSP48E1 ( output [29:0] ACOUT, output [17:0] BCOUT, |