Commit message (Expand) | Author | Age | Files | Lines | |
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* | fix fsm test with proper clock enable polarity | Pepijn de Vos | 2019-11-11 | 1 | -4/+4 |
* | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-11 | 22 | -22988/+30572 |
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| * | synth_xilinx: Merge blackbox primitive libraries. | Marcin Kościelnicki | 2019-11-06 | 11 | -23234/+29820 |
| * | xilinx: Add URAM288 mapping for xcup | David Shah | 2019-10-23 | 5 | -2/+92 |
| * | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 7 | -416/+1062 |
| * | xilinx: Support multiplier mapping for all families. | Marcin Kościelnicki | 2019-10-22 | 9 | -9/+269 |
| * | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg | Clifford Wolf | 2019-10-22 | 2 | -0/+2 |
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| | * | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 2 | -0/+2 |
* | | | fix wide luts | Pepijn de Vos | 2019-11-06 | 1 | -12/+12 |
* | | | add IOBUF | Pepijn de Vos | 2019-10-28 | 2 | -1/+10 |
* | | | add tristate buffer and test | Pepijn de Vos | 2019-10-28 | 2 | -2/+8 |
* | | | More formatting | Pepijn de Vos | 2019-10-28 | 1 | -55/+49 |
* | | | really really fix formatting maybe | Pepijn de Vos | 2019-10-28 | 1 | -41/+41 |
* | | | undo formatting fuckup | Pepijn de Vos | 2019-10-28 | 1 | -25/+25 |
* | | | add wide luts | Pepijn de Vos | 2019-10-28 | 3 | -36/+119 |
* | | | add 32-bit BRAM and byte-enables | Pepijn de Vos | 2019-10-28 | 2 | -4/+25 |
* | | | ALU sim tweaks | Pepijn de Vos | 2019-10-24 | 1 | -11/+11 |
* | | | add a few more missing dff | Pepijn de Vos | 2019-10-21 | 1 | -7/+16 |
* | | | add negedge DFF | Pepijn de Vos | 2019-10-21 | 2 | -15/+139 |
* | | | use ADDSUB ALU mode to remove inverters | Pepijn de Vos | 2019-10-21 | 2 | -7/+77 |
* | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-10-21 | 58 | -1315/+24105 |
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| * | | ecp5: Pass -nomfs to abc9 | David Shah | 2019-10-20 | 1 | -2/+2 |
| * | | Makefile: don't assume python is called `python3` | Sean Cross | 2019-10-19 | 4 | -6/+6 |
| * | | Merge branch 'master' into mmicko/efinix | Miodrag Milanović | 2019-10-18 | 37 | -474/+305 |
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| | * | ecp5: Add ECLKBRIDGECS blackbox | David Shah | 2019-10-11 | 1 | -0/+7 |
| | * | ecp5: Add attrmvcp to copy syn_useioff to driving FF | David Shah | 2019-10-10 | 1 | -0/+1 |
| | * | ecp5: Set syn_useioff on IO FFs to enable packing | David Shah | 2019-10-10 | 1 | -8/+8 |
| | * | xilinx: Add simulation model for IBUFG. | Marcin Kościelnicki | 2019-10-10 | 5 | -33/+14 |
| | * | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 31 | -228/+236 |
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| | | * | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 4 | -181/+9 |
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| | | * | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 31 | -227/+235 |
| | * | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 |
| | * | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 |
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| | * | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -2/+6 |
| | * | | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 3 | -178/+2 |
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| | * | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 5 | -31/+4 |
| | * | Oops | Eddie Hung | 2019-10-04 | 1 | -1/+1 |
| | * | Ohmilord this wasn't added all this time!?! | Eddie Hung | 2019-10-04 | 1 | -0/+29 |
| * | | FF should be initialized to 0 | Miodrag Milanovic | 2019-10-04 | 1 | -1/+3 |
| * | | Add missing latch mapping | Miodrag Milanovic | 2019-10-04 | 1 | -0/+12 |
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| * | ecp5: Fix shuffle_enable port | David Shah | 2019-10-01 | 1 | -2/+2 |
| * | ecp5: Add support for mapping 36-bit wide PDP BRAMs | David Shah | 2019-10-01 | 6 | -1/+183 |
| * | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 6 | -122/+46 |
| * | synth_xilinx: Support latches, remove used-up FF init values. | Marcin Kościelnicki | 2019-09-30 | 2 | -2/+76 |
| * | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 19 | -31/+3395 |
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| | * | Re-order | Eddie Hung | 2019-09-27 | 2 | -2/+2 |
| | * | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
| | * | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once | Eddie Hung | 2019-09-26 | 1 | -9/+4 |
| | * | Typo | Eddie Hung | 2019-09-26 | 1 | -1/+1 |
| | * | select once | Eddie Hung | 2019-09-26 | 2 | -8/+12 |