aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Expand)AuthorAgeFilesLines
* fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-4/+4
* Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1122-22988/+30572
|\
| * synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
| * xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-235-2/+92
| * xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-237-416/+1062
| * xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-229-9/+269
| * Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-222-0/+2
| |\
| | * Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-172-0/+2
* | | fix wide lutsPepijn de Vos2019-11-061-12/+12
* | | add IOBUFPepijn de Vos2019-10-282-1/+10
* | | add tristate buffer and testPepijn de Vos2019-10-282-2/+8
* | | More formattingPepijn de Vos2019-10-281-55/+49
* | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
* | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
* | | add wide lutsPepijn de Vos2019-10-283-36/+119
* | | add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
* | | ALU sim tweaksPepijn de Vos2019-10-241-11/+11
* | | add a few more missing dffPepijn de Vos2019-10-211-7/+16
* | | add negedge DFFPepijn de Vos2019-10-212-15/+139
* | | use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
* | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-10-2158-1315/+24105
|\| |
| * | ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
| * | Makefile: don't assume python is called `python3`Sean Cross2019-10-194-6/+6
| * | Merge branch 'master' into mmicko/efinixMiodrag Milanović2019-10-1837-474/+305
| |\|
| | * ecp5: Add ECLKBRIDGECS blackboxDavid Shah2019-10-111-0/+7
| | * ecp5: Add attrmvcp to copy syn_useioff to driving FFDavid Shah2019-10-101-0/+1
| | * ecp5: Set syn_useioff on IO FFs to enable packingDavid Shah2019-10-101-8/+8
| | * xilinx: Add simulation model for IBUFG.Marcin Kościelnicki2019-10-105-33/+14
| | * Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-0831-228/+236
| | |\
| | | * Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-044-181/+9
| | | |\
| | | * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0431-227/+235
| | * | | Add comment on why partial multipliers are 18x18Eddie Hung2019-10-041-4/+8
| | * | | Fix typo in check_label()Eddie Hung2019-10-041-1/+1
| | | |/ | | |/|
| | * | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-2/+6
| | * | Remove DSP48E1 from *_cells_xtra.vEddie Hung2019-10-043-178/+2
| | |/
| | * Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-045-31/+4
| | * OopsEddie Hung2019-10-041-1/+1
| | * Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
| * | FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3
| * | Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12
| |/
| * ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
| * ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
| * Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
| * synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-302-2/+76
| * Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2919-31/+3395
| |\
| | * Re-orderEddie Hung2019-09-272-2/+2
| | * Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
| | * Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run onceEddie Hung2019-09-261-9/+4
| | * TypoEddie Hung2019-09-261-1/+1
| | * select onceEddie Hung2019-09-262-8/+12
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-26 17:11:35 +0000