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* intel_alm: preliminary Arria V supportLofty2021-11-256-7/+199
* synth_gatemate Revert cascade A/B port mixupPatrick Urban2021-11-132-12/+4
* synth_gatemate: Remove iob_map invokationPatrick Urban2021-11-131-1/+0
* synth_gatemate: Add block RAM cascade supportPatrick Urban2021-11-132-112/+96
* synth_gatemate: Remove obsolete iob_mapPatrick Urban2021-11-133-61/+2
* synth_gatemate: Update passPatrick Urban2021-11-131-65/+25
* synth_gatemate: Remove specify blocksPatrick Urban2021-11-131-92/+0
* synth_gatemate: Remove gatemate_bramopt passPatrick Urban2021-11-133-148/+0
* synth_gatemate: Revise block RAM read modes and initializationPatrick Urban2021-11-133-71/+230
* synth_gatemate: Remove unsupported FF initializationPatrick Urban2021-11-131-2/+0
* synth_gatemate: Rename multiplier factor parametersPatrick Urban2021-11-131-13/+10
* synth_gatemate: Registers are uninitializedPatrick Urban2021-11-132-3/+3
* synth_gatemate: Apply review remarksPatrick Urban2021-11-135-279/+211
* synth_gatemate: Apply review remarksPatrick Urban2021-11-135-141/+86
* synth_gatemate: Initial implementationPatrick Urban2021-11-1315-0/+3716
* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-099-33/+10
* synth_gowin: move splitnets to after iopadmap (#2435)Pepijn de Vos2021-11-071-2/+3
* Remove noalu from synth_gowin json output as Apicula now supports itPepijn de Vos2021-11-071-1/+0
* gowin: widelut support (#3042)Pepijn de Vos2021-11-061-1/+0
* ecp5: Add support for mapping aldff.Marcelina Kościelnicka2021-10-272-13/+13
* Fixed Verific parser error in ice40 cell libraryClaire Xenia Wolf2021-10-191-22/+62
* CycloneV: Add (passthrough) support for cyclonev_oscillatorOlivier Galibert2021-10-171-1/+11
* CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_pu...Olivier Galibert2021-10-171-0/+8
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-1/+1
* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-023-0/+382
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-1/+1
* [ECP5] fix wrong link for syn_* attributes description (#2984)kittennbfive2021-08-292-2/+2
* Add DLLDELDECP5-PCIe2021-08-221-0/+9
* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-204-6/+13
* ice40: Fix typo in SB_CARRY specify for LP/UltraPlusSylvain Munaut2021-08-171-2/+2
* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-0/+169
* Fixes xc7 BRAM36sMaciej Dudek2021-07-301-4/+6
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-1/+1
* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-281-0/+24
* ice40: Fix LUT input indices in opt_lut -dlogic (again).Marcelina Kościelnicka2021-07-101-1/+1
* ecp5: Add DCSC blackboxgatecat2021-07-061-0/+10
* Fix icestorm linksClaire Xenia Wolf2021-06-092-516/+516
* Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-096-6/+6
* Fix files with CRLF line endingsClaire Xenia Wolf2021-06-092-349/+349
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0858-64/+64
* intel_alm: Fix illegal carry chainsgatecat2021-05-152-3/+5
* intel_alm: Add global buffer insertiongatecat2021-05-156-4/+78
* intel_alm: Add IO buffer insertiongatecat2021-05-156-7/+127
* Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.Adam Greig2021-05-121-0/+22
* Fix use of blif name in synth_xilinx commandMichael Christensen2021-04-271-1/+1
* Add default assignments to other SB_* simulation modelsClaire Xenia Wolf2021-04-201-24/+44
* Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-201-1/+17
* quicklogic: ABC9 synthesisLofty2021-04-176-5/+80
* sf2: fix name of AND modulesStefan Riesenberger2021-04-091-3/+3
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-292-0/+9
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