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Author
Age
Files
Lines
*
xilinx: Use dfflegalize.
Marcelina Kościelnicka
2020-07-09
6
-484
/
+131
*
efinix: Use dfflegalize.
Marcelina Kościelnicka
2020-07-06
2
-15
/
+53
*
gowin: Use dfflegalize.
Marcelina Kościelnicka
2020-07-06
2
-145
/
+41
*
intel_alm: direct M10K instantiation
Dan Ravensloft
2020-07-05
7
-38
/
+122
*
synth_gowin: ABC9 support
Dan Ravensloft
2020-07-05
2
-34
/
+340
*
Merge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40
Marcelina Kościelnicka
2020-07-05
4
-208
/
+24
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\
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*
ice40: Use dfflegalize.
Marcelina Kościelnicka
2020-07-05
4
-208
/
+24
*
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ecp5: Use dfflegalize.
Marcelina Kościelnicka
2020-07-05
4
-254
/
+96
*
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Merge pull request #2232 from YosysHQ/mwk/gowin-sim-init
Marcelina Kościelnicka
2020-07-05
1
-8
/
+8
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\
\
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*
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gowin: Fix INIT values in sim library.
Marcelina Kościelnicka
2020-07-05
1
-8
/
+8
*
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intel_alm: DSP inference
Dan Ravensloft
2020-07-05
6
-9
/
+186
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/
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/
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*
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gowin: replace determine_init with setundef
Dan Ravensloft
2020-07-04
3
-74
/
+1
*
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synth_intel_alm: Use dfflegalize.
Marcelina Kościelnicka
2020-07-04
2
-121
/
+9
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/
*
Improve MISTRAL_FF specify rules
Dan Ravensloft
2020-07-04
1
-5
/
+4
*
intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
Eddie Hung
2020-07-04
2
-47
/
+2
*
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
Eddie Hung
2020-07-04
4
-4
/
+4
*
intel_alm: ABC9 sequential optimisations
Dan Ravensloft
2020-07-04
7
-19
/
+149
*
simcells: Fix reset polarity for $_DLATCH_???_ cells.
Marcelina Kościelnicka
2020-06-30
2
-5
/
+5
*
Update dff2dffe, dff2dffs, zinit to new FF types.
Marcelina Kościelnicka
2020-06-23
16
-128
/
+128
*
Add new FF types to simplemap.
Marcelina Kościelnicka
2020-06-23
1
-1
/
+1
*
Add new builtin FF types
Marcelina Kościelnicka
2020-06-23
3
-0
/
+2293
*
Use C++11 final/override keywords.
whitequark
2020-06-18
31
-95
/
+95
*
Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
Xark
2020-06-14
1
-7
/
+7
*
intel_alm: fix DFFE matching
Dan Ravensloft
2020-06-11
1
-1
/
+1
*
Do not optimize away FFs in "prep" and Verific fron-end
Claire Wolf
2020-06-09
1
-2
/
+2
*
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
Eddie Hung
2020-06-04
1
-1
/
+1
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\
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*
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
Eddie Hung
2020-05-29
1
-1
/
+1
*
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Add flooring division operator
Xiretza
2020-05-28
2
-0
/
+71
*
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Add flooring modulo operator
Xiretza
2020-05-28
2
-3
/
+124
*
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xilinx: tidy up cells_sim.v a little
Eddie Hung
2020-05-25
1
-5
/
+7
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/
*
ecp5: cleanup unused +/ecp5/abc9_model.v
Eddie Hung
2020-05-23
3
-14
/
+0
*
Add force_downto and force_upto wire attributes.
Marcelina Kościelnicka
2020-05-19
39
-24
/
+232
*
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
Eddie Hung
2020-05-14
2
-14
/
+2
*
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
Eddie Hung
2020-05-14
2
-5
/
+4
*
abc9_ops/xaiger: further reducing Module::derive() calls by ...
Eddie Hung
2020-05-14
2
-7
/
+5
*
Cleanup; reduce Module::derive() calls
Eddie Hung
2020-05-14
2
-4
/
+4
*
ecp5: latches_map.v if *not* -asyncprld
Eddie Hung
2020-05-14
1
-2
/
+2
*
ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v
Eddie Hung
2020-05-14
4
-43
/
+3
*
ecp5: fix rebase mistake
Eddie Hung
2020-05-14
1
-3
/
+3
*
xilinx: gate specify/attributes from iverilog
Eddie Hung
2020-05-14
1
-1
/
+3
*
abc9: only do +/abc9_map if `DFF
Eddie Hung
2020-05-14
1
-0
/
+2
*
ecp5: TRELLIS_FF bypass path only in async mode
Eddie Hung
2020-05-14
1
-8
/
+8
*
xilinx/ice40/ecp5: zinit requires selected wires, so select them all
Eddie Hung
2020-05-14
3
-4
/
+4
*
xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells
Eddie Hung
2020-05-14
3
-4
/
+198
*
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
Eddie Hung
2020-05-14
8
-763
/
+129
*
abc9: not enough to techmap_fail on (* init=1 *), hide them using $__
Eddie Hung
2020-05-14
2
-10
/
+26
*
synth_*: no need to explicitly read +/abc9_model.v
Eddie Hung
2020-05-14
4
-4
/
+3
*
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
Eddie Hung
2020-05-14
4
-0
/
+55
*
abc9_ops: -prep_dff_map to error if async flop found
Eddie Hung
2020-05-14
1
-4
/
+0
*
Uncomment negative setup times; clamp to zero for connectivity
Eddie Hung
2020-05-14
1
-13
/
+29
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