Add new builtin FF types

The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).

3 files changed, 2293 insertions, 0 deletions

diff --git a/techlibs/common/gen_fine_ffs.py b/techlibs/common/gen_fine_ffs.py
index 0abe48f61..e92d58f40 100644
--- a/techlibs/common/gen_fine_ffs.py
+++ b/techlibs/common/gen_fine_ffs.py
@@ -108,6 +108,31 @@ endmodule
 """
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
+//-     $_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity {V:reset|set} and {E:negative|positive}
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - {R:0|1} - | {V:0|1}
+//-                 d {C:\\|/} - {E:0|1} | d
+//-                 - - - - | q
+//-
+module \$_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @({C:neg|pos}edge C or {R:neg|pos}edge R) begin
+	if (R == {R:0|1})
+		Q <= {V:0|1};
+	else if (E == {E:0|1})
+		Q <= D;
+end
+endmodule
+""",
+"""
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
 //-     $_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q)
 //-
 //- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set and {R:negative|positive}
@@ -136,6 +161,110 @@ endmodule
 """
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
+//-     $_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set, {R:negative|positive}
+//- polarity reset and {E:negative|positive} polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - {R:0|1} - - | 0
+//-                 - {S:0|1} - - - | 1
+//-                 {C:\\|/} - - {E:0|1} d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @({C:neg|pos}edge C, {S:neg|pos}edge S, {R:neg|pos}edge R) begin
+	if (R == {R:0|1})
+		Q <= 0;
+	else if (S == {S:0|1})
+		Q <= 1;
+        else if (E == {E:0|1})
+		Q <= D;
+end
+endmodule
+""",
+"""
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set}.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - {C:\\|/} {R:0|1} | {V:0|1}
+//-                 d {C:\\|/} - | d
+//-                 - - - | q
+//-
+module \$_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @({C:neg|pos}edge C) begin
+	if (R == {R:0|1})
+		Q <= {V:0|1};
+	else
+		Q <= D;
+end
+endmodule
+""",
+"""
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
+//- polarity clock enable (with {V:reset|set} having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - {C:\\|/} {R:0|1} - | {V:0|1}
+//-                 d {C:\\|/} - {E:0|1} | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @({C:neg|pos}edge C) begin
+	if (R == {R:0|1})
+		Q <= {V:0|1};
+	else if (E == {E:0|1})
+		Q <= D;
+end
+endmodule
+""",
+"""
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - {C:\\|/} {R:0|1} {E:0|1} | {V:0|1}
+//-                 d {C:\\|/} - {E:0|1} | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @({C:neg|pos}edge C) begin
+	if (E == {E:0|1}) begin
+		if (R == {R:0|1})
+			Q <= {V:0|1};
+		else
+			Q <= D;
+	end
+end
+endmodule
+""",
+"""
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
 //-     $_DLATCH_{E:N|P}_ (E, D, Q)
 //-
 //- A {E:negative|positive} enable D-type latch.
@@ -157,6 +286,30 @@ endmodule
 """
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
+//-     $_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q)
+//-
+//- A {E:negative|positive} enable D-type latch with {R:negative|positive} polarity {V:reset|set}.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - {R:0|1} - | {V:0|1}
+//-                 {E:0|1} - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == {E:0|1})
+                Q <= {V:0|1};
+	else if (E == {E:0|1})
+		Q <= D;
+end
+endmodule
+""",
+"""
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
 //-     $_DLATCHSR_{E:N|P}{S:N|P}{R:N|P}_ (E, S, R, D, Q)
 //-
 //- A {E:negative|positive} enable D-type latch with {S:negative|positive} polarity set and {R:negative|positive}
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 157e8d23b..01b5bdfa6 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -870,6 +870,390 @@ endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
+//-     $_DFFE_NN0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 0
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 0
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_NN1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 1
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 0
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_NP0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 0
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_NP1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 1
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_PN0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 0
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_PN0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 0
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_PN1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 0 - | 1
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_PP0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 0
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_PP0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 0
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_PP1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - - 1 - | 1
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_DFFE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
 //-     $_DFFSR_NNN_ (C, S, R, D, Q)
 //-
 //- A negative edge D-type flip-flop with negative polarity set and negative
@@ -1086,6 +1470,1422 @@ endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
+//-     $_DFFSRE_NNNN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 0 - - - | 1
+//-                 \ - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NNNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NNNP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 0 - - - | 1
+//-                 \ - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NNPN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 0 - - - | 1
+//-                 \ - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NNPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NNPP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 0 - - - | 1
+//-                 \ - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NNPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NPNN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 1 - - - | 1
+//-                 \ - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NPNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NPNP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 1 - - - | 1
+//-                 \ - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NPNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NPPN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 1 - - - | 1
+//-                 \ - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NPPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_NPPP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 1 - - - | 1
+//-                 \ - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_NPPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PNNN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 0 - - - | 1
+//-                 / - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PNNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PNNP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 0 - - - | 1
+//-                 / - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PNPN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 0 - - - | 1
+//-                 / - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PNPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PNPP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 0 - - - | 1
+//-                 / - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PNPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 0)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PPNN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 1 - - - | 1
+//-                 / - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PPNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PPNP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 0 - - | 0
+//-                 - 1 - - - | 1
+//-                 / - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PPNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, negedge R) begin
+	if (R == 0)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PPPN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 1 - - - | 1
+//-                 / - - 0 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PPPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DFFSRE_PPPP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table:    C S R E D | Q
+//-                -----------+---
+//-                 - - 1 - - | 0
+//-                 - 1 - - - | 1
+//-                 / - - 1 d | d
+//-                 - - - - - | q
+//-
+module \$_DFFSRE_PPPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, posedge R) begin
+	if (R == 1)
+		Q <= 0;
+	else if (S == 1)
+		Q <= 1;
+        else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_NN0_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - \ 0 | 0
+//-                 d \ - | d
+//-                 - - - | q
+//-
+module \$_SDFF_NN0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_NN1_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - \ 0 | 1
+//-                 d \ - | d
+//-                 - - - | q
+//-
+module \$_SDFF_NN1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_NP0_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - \ 1 | 0
+//-                 d \ - | d
+//-                 - - - | q
+//-
+module \$_SDFF_NP0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_NP1_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - \ 1 | 1
+//-                 d \ - | d
+//-                 - - - | q
+//-
+module \$_SDFF_NP1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_PN0_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - / 0 | 0
+//-                 d / - | d
+//-                 - - - | q
+//-
+module \$_SDFF_PN0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_PN1_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - / 0 | 1
+//-                 d / - | d
+//-                 - - - | q
+//-
+module \$_SDFF_PN1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_PP0_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - / 1 | 0
+//-                 d / - | d
+//-                 - - - | q
+//-
+module \$_SDFF_PP0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFF_PP1_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set.
+//-
+//- Truth table:    D C R | Q
+//-                -------+---
+//-                 - / 1 | 1
+//-                 d / - | d
+//-                 - - - | q
+//-
+module \$_SDFF_PP1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NN0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 - | 0
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 - | 0
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 - | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NN1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 - | 1
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 - | 0
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NP0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 - | 0
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 - | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_NP1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 - | 1
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PN0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 - | 0
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PN0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 - | 0
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 - | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PN1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 - | 1
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 0)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PP0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 - | 0
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PP0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 - | 0
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PP1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 - | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 - | 1
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (R == 1)
+		Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NN0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 0 | 0
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 0) begin
+		if (R == 0)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 1 | 0
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 1) begin
+		if (R == 0)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 0 | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 0) begin
+		if (R == 0)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NN1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 0 1 | 1
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 1) begin
+		if (R == 0)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 0 | 0
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 0) begin
+		if (R == 1)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NP0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 1 | 0
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 1) begin
+		if (R == 1)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 0 | 1
+//-                 d \ - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 0) begin
+		if (R == 1)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_NP1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - \ 1 1 | 1
+//-                 d \ - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+	if (E == 1) begin
+		if (R == 1)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PN0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 0 | 0
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 0) begin
+		if (R == 0)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PN0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 1 | 0
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 1) begin
+		if (R == 0)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 0 | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 0) begin
+		if (R == 0)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PN1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 0 1 | 1
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 1) begin
+		if (R == 0)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PP0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 0 | 0
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 0) begin
+		if (R == 1)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PP0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 1 | 0
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 1) begin
+		if (R == 1)
+			Q <= 0;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PP1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 0 | 1
+//-                 d / - 0 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 0) begin
+		if (R == 1)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_SDFFCE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table:    D C R E | Q
+//-                ---------+---
+//-                 - / 1 1 | 1
+//-                 d / - 1 | d
+//-                 - - - - | q
+//-
+module \$_SDFFCE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+	if (E == 1) begin
+		if (R == 1)
+			Q <= 1;
+		else
+			Q <= D;
+	end
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
 //-     $_DLATCH_N_ (E, D, Q)
 //-
 //- A negative enable D-type latch.
@@ -1126,6 +2926,190 @@ endmodule
 
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
+//-     $_DLATCH_NN0_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with negative polarity reset.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 0 - | 0
+//-                 0 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_NN0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+                Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_NN1_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with negative polarity set.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 0 - | 1
+//-                 0 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_NN1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+                Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_NP0_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with positive polarity reset.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 1 - | 0
+//-                 0 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_NP0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+                Q <= 0;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_NP1_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with positive polarity set.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 1 - | 1
+//-                 0 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_NP1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 0)
+                Q <= 1;
+	else if (E == 0)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_PN0_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with negative polarity reset.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 0 - | 0
+//-                 1 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_PN0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+                Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_PN1_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with negative polarity set.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 0 - | 1
+//-                 1 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_PN1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+                Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_PP0_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with positive polarity reset.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 1 - | 0
+//-                 1 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_PP0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+                Q <= 0;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//-     $_DLATCH_PP1_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with positive polarity set.
+//-
+//- Truth table:    E R D | Q
+//-                -------+---
+//-                 - 1 - | 1
+//-                 1 - d | d
+//-                 - - - | q
+//-
+module \$_DLATCH_PP1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+	if (R == 1)
+                Q <= 1;
+	else if (E == 1)
+		Q <= D;
+end
+endmodule
+
+//  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
 //-     $_DLATCHSR_NNN_ (E, S, R, D, Q)
 //-
 //- A negative enable D-type latch with negative polarity set and negative
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 125b8e013..2660e6f15 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1822,6 +1822,39 @@ endgenerate
 
 endmodule
 
+// --------------------------------------------------------
+
+module \$dffsre (CLK, SET, CLR, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter SET_POLARITY = 1'b1;
+parameter CLR_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+
+input CLK, EN;
+input [WIDTH-1:0] SET, CLR, D;
+output reg [WIDTH-1:0] Q;
+
+wire pos_clk = CLK == CLK_POLARITY;
+wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
+wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
+
+genvar i;
+generate
+	for (i = 0; i < WIDTH; i = i+1) begin:bitslices
+		always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
+			if (pos_clr[i])
+				Q[i] <= 0;
+			else if (pos_set[i])
+				Q[i] <= 1;
+			else if (EN == EN_POLARITY)
+				Q[i] <= D[i];
+	end
+endgenerate
+
+endmodule
+
 `endif
 // --------------------------------------------------------
 
@@ -1849,6 +1882,107 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$sdff (CLK, SRST, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter SRST_POLARITY = 1'b1;
+parameter SRST_VALUE = 0;
+
+input CLK, SRST;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_srst = SRST == SRST_POLARITY;
+
+always @(posedge pos_clk) begin
+	if (pos_srst)
+		Q <= SRST_VALUE;
+	else
+		Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$adffe (CLK, ARST, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+parameter ARST_POLARITY = 1'b1;
+parameter ARST_VALUE = 0;
+
+input CLK, ARST, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_arst = ARST == ARST_POLARITY;
+
+always @(posedge pos_clk, posedge pos_arst) begin
+	if (pos_arst)
+		Q <= ARST_VALUE;
+	else if (EN == EN_POLARITY)
+		Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$sdffe (CLK, SRST, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+parameter SRST_POLARITY = 1'b1;
+parameter SRST_VALUE = 0;
+
+input CLK, SRST, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_srst = SRST == SRST_POLARITY;
+
+always @(posedge pos_clk) begin
+	if (pos_srst)
+		Q <= SRST_VALUE;
+	else if (EN == EN_POLARITY)
+		Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$sdffce (CLK, SRST, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+parameter SRST_POLARITY = 1'b1;
+parameter SRST_VALUE = 0;
+
+input CLK, SRST, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_srst = SRST == SRST_POLARITY;
+
+always @(posedge pos_clk) begin
+	if (EN == EN_POLARITY) begin
+		if (pos_srst)
+			Q <= SRST_VALUE;
+		else
+			Q <= D;
+	end
+end
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$dlatch (EN, D, Q);
 
 parameter WIDTH = 0;
@@ -1866,6 +2000,28 @@ end
 endmodule
 
 // --------------------------------------------------------
+
+module \$adlatch (EN, ARST, D, Q);
+
+parameter WIDTH = 0;
+parameter EN_POLARITY = 1'b1;
+parameter ARST_POLARITY = 1'b1;
+parameter ARST_VALUE = 0;
+
+input EN, ARST;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+
+always @* begin
+	if (ARST == ARST_POLARITY)
+		Q = ARST_VALUE;
+	else if (EN == EN_POLARITY)
+		Q = D;
+end
+
+endmodule
+
+// --------------------------------------------------------
 `ifndef SIMLIB_NOSR
 
 module \$dlatchsr (EN, SET, CLR, D, Q);