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* fix BRAM width and initPepijn de Vos2019-09-062-12/+28
* add more DFF to sim libPepijn de Vos2019-09-062-6/+111
* WIP aditional DFF primitivesPepijn de Vos2019-09-052-1/+48
* support bram initialisationPepijn de Vos2019-09-055-3/+25
* use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
* add MUX supportPepijn de Vos2019-09-053-0/+17
* set undriven pads to zeroPepijn de Vos2019-09-041-0/+1
* Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
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| * Updating gowinDiego H2019-09-022-2/+2
* | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
* | Fix TRELLIS_FF simulation modelMiodrag Milanovic2019-08-311-6/+7
* | ecp5_gsr: Fix typoDavid Shah2019-08-311-1/+1
* | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-3013-136/+180
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| * | ecp5: Add simulation equivalence check for Diamond FF implementationsDavid Shah2019-08-303-0/+87
| * | ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.whitequark2019-08-305-95/+60
| * | ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives.whitequark2019-08-301-35/+20
| * | ecp5: add missing FD primitives.whitequark2019-08-302-72/+76
| * | ecp5: fix CEMUX on IFS/OFS primitives.whitequark2019-08-302-18/+18
| * | Rename boxes tooEddie Hung2019-08-293-3/+3
| * | Do not overwrite LUT paramEddie Hung2019-08-281-1/+0
| * | Trailing commaEddie Hung2019-08-281-1/+1
| * | Adapt to $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-3/+5
| * | Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with"Eddie Hung2019-08-281-0/+45
| * | Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason withEddie Hung2019-08-281-45/+0
| * | Update box size and timingsEddie Hung2019-08-283-12/+12
| * | Update to new $__ICE40_CARRY_WRAPPEREddie Hung2019-08-281-11/+8
| * | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendorEddie Hung2019-08-281-3/+8
* | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-2813-248/+835
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| * | Merge pull request #1332 from YosysHQ/dave/ecp5gsrDavid Shah2019-08-286-54/+212
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| | * | ecp5: Add GSR supportDavid Shah2019-08-276-54/+212
| * | | xilinx: Add SRLC16E primitive.Marcin Kościelnicki2019-08-271-1/+21
| * | | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-261-0/+8
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| * | | Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-231-1/+1
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| * \ \ \ Merge branch 'master' into mwk/xilinx_bufgmapEddie Hung2019-08-233-18/+36
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| * \ \ \ \ Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmapEddie Hung2019-08-2329-299/+1059
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| * | | | | | move attributes to wiresMarcin Kościelnicki2019-08-136-283/+537
| * | | | | | minor review fixesMarcin Kościelnicki2019-08-131-1/+1
| * | | | | | review fixesMarcin Kościelnicki2019-08-131-18/+27
| * | | | | | Add clock buffer insertion pass, improve iopadmap.Marcin Kościelnicki2019-08-136-71/+220
* | | | | | | Merge branch 'master' into eddie/xilinx_srlEddie Hung2019-08-261-0/+8
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| * | | | | | Add undocumented featureEddie Hung2019-08-231-0/+8
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* | | | | | xilinx_srl now copes with word-level flops $dff{,e}Eddie Hung2019-08-231-8/+3
* | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-233-15/+30
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| * | | | | Forgot oneEddie Hung2019-08-231-1/+2
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| * | | | Put abc_* attributes above portEddie Hung2019-08-233-14/+28
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* | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srlEddie Hung2019-08-2214-92/+961
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| * | | Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
| * | | Merge pull request #1289 from mmicko/anlogic_fixesClifford Wolf2019-08-225-91/+162
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| | * \ \ Merge remote-tracking branch 'upstream/master' into anlogic_fixesMiodrag Milanovic2019-08-187-165/+37
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| | * | | Proper arith for Anlogic and use standard passMiodrag Milanovic2019-08-125-91/+162
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