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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 18:45:09 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 18:46:53 -0700 |
| commit | a4f641f2303bc6f04751a15ec49cf2658ea8eb63 (patch) | |
| tree | 369f9932a623f18f5a2878f399b54687c8bbdafe /techlibs | |
| parent | e301a3dadbc81a300443713cf7877ea24cc0b2b2 (diff) | |
| download | yosys-a4f641f2303bc6f04751a15ec49cf2658ea8eb63.tar.gz yosys-a4f641f2303bc6f04751a15ec49cf2658ea8eb63.tar.bz2 yosys-a4f641f2303bc6f04751a15ec49cf2658ea8eb63.zip | |
Do not overwrite LUT param
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 58f106f7c..ea56d3f4d 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -125,7 +125,6 @@ static void run_ice40_opts(Module *module) cell->unsetPort("\\I3"); cell->unsetPort("\\CO"); cell->unsetPort("\\O"); - cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110")); cell->setParam("\\WIDTH", 4); } continue; |