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* Valid to have attribute starting with SB_CARRY.Miodrag Milanovic2020-01-041-0/+2
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* Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-0218-40/+67
|\ | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-0118-40/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
* | Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-0212-37/+37
|\ \ | | | | | | "abc -dff" to no longer retime by default
| * | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-3011-12/+12
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| * | Disable synth_gowin -abc9 as it offers no advantages yetEddie Hung2019-12-301-12/+12
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| * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-3011-13/+13
| | | | | | | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* | | ifdef __ICARUS__ -> ifndef YOSYSEddie Hung2020-01-011-6/+6
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* | | Fix anlogic async flop mappingEddie Hung2020-01-011-8/+8
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* | Update timings for Xilinx S7 cellsEddie Hung2019-12-301-15/+35
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* | Merge pull request #1589 from YosysHQ/iopad_defaultMiodrag Milanović2019-12-301-11/+6
|\ \ | |/ |/| Make iopad option default for all xilinx flows
| * Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-288-10/+368
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| * | Addressed review commentsMiodrag Milanovic2019-12-211-2/+3
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| * | iopad no op for compatibility with old scriptsMiodrag Milanovic2019-12-211-0/+3
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| * | Make iopad option default for all xilinx flowsMiodrag Milanovic2019-12-211-14/+5
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* | | Nitpick cleanup for ecp5Eddie Hung2019-12-272-11/+3
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* | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgenMarcin Kościelnicki2019-12-253-3/+6
|\ \ | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support.
| * | xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-223-3/+6
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* / xilinx: Test our DSP48A/DSP48A1 simulation models.Marcin Kościelnicki2019-12-235-7/+362
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* Add abc9_arrival times for RAM{32,64}MEddie Hung2019-12-201-24/+10
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* Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-201-0/+78
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* Revert "Optimise write_xaiger"Eddie Hung2019-12-203-15/+0
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* Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-193-0/+15
|\ | | | | Optimise write_xaiger
| * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-063-0/+15
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* | xilinx: Add simulation models for remaining CLB primitives.Marcin Kościelnicki2019-12-193-156/+210
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* | xilinx_dffopt: Keep order of LUT inputs.Marcin Kościelnicki2019-12-191-16/+30
| | | | | | | | See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
* | Merge pull request #1563 from YosysHQ/dave/async-prldDavid Shah2019-12-182-4/+28
|\ \ | | | | | | ecp5: Add support for mapping PRLD FFs
| * | ecp5: Add support for mapping PRLD FFsDavid Shah2019-12-072-4/+28
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-186-22/+389
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* | xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-184-38/+228
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
* | Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-163-12/+301
|\ \ | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M
| * \ Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into ↵Eddie Hung2019-12-161-2/+8
| |\ \ | | | | | | | | | | | | eddie/xilinx_lutram
| | * | Populate DID/DOD even if unusedEddie Hung2019-12-161-2/+8
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| * | | Rename *RAM{32,64}M rules to RAM{32X2,64X1}QEddie Hung2019-12-162-6/+6
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| * | Disable RAM16X1D match rule; carry-over from LUT4 archesEddie Hung2019-12-131-6/+9
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| * | RAM64M8 to also have [5:0] for addressEddie Hung2019-12-131-8/+8
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| * | Add RAM32X6SDP and RAM64X3SDP modesEddie Hung2019-12-122-8/+120
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| * | Fix RAM64M model to have 6 bit address busEddie Hung2019-12-121-4/+4
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| * | Add memory rules for RAM16X1D, RAM32M, RAM64MEddie Hung2019-12-122-0/+168
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* | | Add unconditional match blocks for force RAMEddie Hung2019-12-161-4/+36
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* | | Update xc7/xcu bram rulesEddie Hung2019-12-161-8/+4
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* | | Removing fixed attribute value to !ramstyle rulesDiego H2019-12-151-4/+4
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* | | Merging attribute rules into a single match block; Adding testsDiego H2019-12-151-18/+12
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* | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specificDiego H2019-12-131-0/+19
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* | | Merge pull request #1533 from dh73/bram_xilinxEddie Hung2019-12-131-6/+9
|\ \ \ | |/ / |/| | Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
| * | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-121-5/+5
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| * | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-121-2/+2
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| * | Merge https://github.com/YosysHQ/yosys into bram_xilinxDiego H2019-12-1220-775/+1170
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| * | | Adjusting Vivado's BRAM min bits threshold for RAMB18E1Diego H2019-11-271-2/+5
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* | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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