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* Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xil...Eddie Hung2019-12-161-2/+8
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| * Populate DID/DOD even if unusedEddie Hung2019-12-161-2/+8
* | Rename *RAM{32,64}M rules to RAM{32X2,64X1}QEddie Hung2019-12-162-6/+6
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* Disable RAM16X1D match rule; carry-over from LUT4 archesEddie Hung2019-12-131-6/+9
* RAM64M8 to also have [5:0] for addressEddie Hung2019-12-131-8/+8
* Add RAM32X6SDP and RAM64X3SDP modesEddie Hung2019-12-122-8/+120
* Fix RAM64M model to have 6 bit address busEddie Hung2019-12-121-4/+4
* Add memory rules for RAM16X1D, RAM32M, RAM64MEddie Hung2019-12-122-0/+168
* abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
* Fix bitwidth mismatch; suppresses iverilog warningEddie Hung2019-12-111-4/+4
* Merge pull request #1564 from ZirconiumX/intel_housekeepingDavid Shah2019-12-118-6/+6
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| * synth_intel: a10gx -> arria10gxDan Ravensloft2019-12-105-4/+4
| * synth_intel: cyclone10 -> cyclone10lpDan Ravensloft2019-12-105-4/+4
* | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-094-20/+22
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| * ice40_opt to restore attributes/name when unwrappingEddie Hung2019-12-091-0/+15
| * Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-091-1/+1
| * ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-092-19/+1
| * $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserveEddie Hung2019-12-031-1/+1
| * ice40_opt to ignore (* keep *) -ed cellsEddie Hung2019-12-031-0/+5
* | xilinx: Add tristate buffer mapping. (#1528)Marcin Kościelnicki2019-12-042-9/+16
* | xilinx: Add models for LUTRAM cells. (#1537)Marcin Kościelnicki2019-12-043-624/+831
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* Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-032-112/+270
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| * Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-1/+1
| * attempt to fix formattingPepijn de Vos2019-11-251-154/+154
| * gowin: add and test dff init valuesPepijn de Vos2019-11-252-41/+199
* | xilinx: Add missing blackbox cell for BUFPLL.Marcin Kościelnicki2019-11-292-0/+21
* | xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-263-25/+30
* | clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-1/+5
* | xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-251-2/+6
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* coolrunner2: remove spurious log_pop() call, fixes #1463Martin Pietryka2019-11-231-2/+0
* gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
* Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-198-43/+547
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| * Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| * add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
| * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-164-15/+439
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| * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-4/+4
| * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1122-22988/+30572
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| * | | fix wide lutsPepijn de Vos2019-11-061-12/+12
| * | | add IOBUFPepijn de Vos2019-10-282-1/+10
| * | | add tristate buffer and testPepijn de Vos2019-10-282-2/+8
| * | | More formattingPepijn de Vos2019-10-281-55/+49
| * | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
| * | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
| * | | add wide lutsPepijn de Vos2019-10-283-36/+119
| * | | add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
| * | | ALU sim tweaksPepijn de Vos2019-10-241-11/+11
| * | | add a few more missing dffPepijn de Vos2019-10-211-7/+16
| * | | add negedge DFFPepijn de Vos2019-10-212-15/+139
| * | | use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
| * | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-10-2158-1315/+24105
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