| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Blackboxes | Eddie Hung | 2019-05-26 | 2 | -10/+10 |
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| * | Muck about with LUT delays some more | Eddie Hung | 2019-05-26 | 1 | -5/+5 |
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| * | Try new LUT delays | Eddie Hung | 2019-05-24 | 1 | -8/+11 |
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| * | Transpose CARRY4 delays | Eddie Hung | 2019-05-24 | 1 | -10/+8 |
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| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-23 | 1 | -0/+4 |
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| | * | Add "min bits" and "min wports" to xilinx dram rules | Eddie Hung | 2019-05-23 | 1 | -0/+4 |
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| * | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux | Eddie Hung | 2019-05-23 | 1 | -2/+4 |
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| | * | Add "wreduce -keepdc", fixes #1016 | Clifford Wolf | 2019-05-20 | 1 | -2/+4 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Add whitebox support to DRAM | Eddie Hung | 2019-05-23 | 5 | -24/+26 |
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| * | | shift register inference before mux | Eddie Hung | 2019-05-22 | 1 | -3/+3 |
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| * | | Fix/workaround symptom unveiled by #1023 | Eddie Hung | 2019-05-21 | 1 | -4/+14 |
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| * | | Instead of MUXCY/XORCY use CARRY4 (with timing) | Eddie Hung | 2019-05-21 | 4 | -11/+20 |
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| * | | Modify LUT area cost to be same as old abc | Eddie Hung | 2019-05-21 | 1 | -10/+9 |
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| * | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-21 | 5 | -230/+421 |
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| | * | ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC | Sylvain Munaut | 2019-05-13 | 1 | -0/+11 |
| | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| | * | Add "stat -tech xilinx" | Clifford Wolf | 2019-05-11 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Fix formatting for synth_intel.cc | Ben Widawsky | 2019-05-09 | 1 | -222/+211 |
| | | | | | | | | | | | | | This is realized through the recently added .clang-format file. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| | * | Add "synth_xilinx -arch" | Clifford Wolf | 2019-05-07 | 1 | -1/+13 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 6 | -178/+124 |
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| | | * | Rename cells_map.v to prevent clash with ff_map.v | Eddie Hung | 2019-05-03 | 1 | -6/+8 |
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| | | * | Merge pull request #969 from YosysHQ/clifford/pmgenstuff | Clifford Wolf | 2019-05-03 | 2 | -0/+4 |
| | | |\ | | | | | | | | | Improve pmgen, Add "peepopt" pass with shift-mul pattern | ||||
| | * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -3/+4 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -0/+28 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵ | Clifford Wolf | 2019-04-23 | 1 | -70/+70 |
| | | | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Add $specify2 and $specify3 cells to simlib | Clifford Wolf | 2019-04-23 | 1 | -0/+147 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Trim off leading 1'bx in A | Eddie Hung | 2019-05-02 | 1 | -7/+20 |
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| * | | | | Add don't care optimisation | Eddie Hung | 2019-05-02 | 1 | -0/+11 |
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| * | | | | Use new peepopt from #969 | Eddie Hung | 2019-05-02 | 1 | -10/+15 |
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| * | | | | Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux | Eddie Hung | 2019-05-02 | 2 | -0/+4 |
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| | * | | | Run "peepopt" in generic "synth" pass and "synth_ice40" | Clifford Wolf | 2019-04-30 | 2 | -0/+4 |
| | |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Revert to pre-muxcover approach | Eddie Hung | 2019-05-02 | 2 | -25/+82 |
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| * | | | Missing help_mode | Eddie Hung | 2019-05-02 | 1 | -1/+1 |
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| * | | | Fix -nocarry | Eddie Hung | 2019-05-02 | 1 | -3/+3 |
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| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-02 | 5 | -181/+123 |
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| | * | | Back to passing all xc7srl tests! | Eddie Hung | 2019-05-01 | 1 | -5/+4 |
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| | * | | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine | Eddie Hung | 2019-05-01 | 3 | -170/+104 |
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| | | * \ | Merge pull request #966 from YosysHQ/clifford/fix956 | Clifford Wolf | 2019-04-30 | 1 | -1/+1 |
| | | |\ \ | | | | | | | | | | | Drive dangling wires with init attr with their init value | ||||
| | | | * | | Add handling of init attributes in "opt_expr -undriven" | Clifford Wolf | 2019-04-30 | 1 | -1/+1 |
| | | | |/ | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | | * | | Refactor synth_xilinx to auto-generate doc | Eddie Hung | 2019-04-26 | 1 | -153/+95 |
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| | | * | | Cleanup ice40 | Eddie Hung | 2019-04-26 | 1 | -4/+6 |
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| | * | | WIP | Eddie Hung | 2019-04-28 | 1 | -36/+22 |
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| | * | | Move neg-pol to pos-pol mapping from ff_map to cells_map.v | Eddie Hung | 2019-04-28 | 2 | -9/+12 |
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| | * | | Revert synth_xilinx 'fine' label more to how it used to be... | Eddie Hung | 2019-04-26 | 1 | -21/+40 |
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| * | | | Fix spacing | Eddie Hung | 2019-04-26 | 1 | -4/+4 |
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| * | | | Apparently, this reduces number of MUXCY/XORCY | Eddie Hung | 2019-04-26 | 1 | -10/+9 |
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| * | | | Try a different approach with 'muxcover' | Eddie Hung | 2019-04-26 | 2 | -88/+36 |
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| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-04-26 | 1 | -1/+0 |
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| | * | | Where did this check come from!?! | Eddie Hung | 2019-04-26 | 1 | -1/+0 |
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| * | | Remove split_shiftx call | Eddie Hung | 2019-04-26 | 1 | -4/+1 |
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index : iCE40/yosys | |
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