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* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-035-13/+121
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| * cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmpEddie Hung2020-04-031-1/+1
| * cmp2lcu: fail if `LUT_WIDTH < 2Eddie Hung2020-04-031-1/+1
| * synth: only techmap cmp2{lut,lcu} if -lutEddie Hung2020-04-031-1/+1
| * synth: use +/cmp2lcu.v in generic 'synth' tooEddie Hung2020-04-031-2/+2
| * Cleanup +/cmp2lut.vEddie Hung2020-04-031-8/+0
| * synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse'Eddie Hung2020-04-031-2/+1
| * +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-33/+42
| * Refactor +/cmp2lcu.v into recursive techmapEddie Hung2020-04-031-38/+65
| * CleanupEddie Hung2020-04-031-31/+28
| * Cleanup cmp2lcu.vEddie Hung2020-04-031-16/+16
| * techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcuEddie Hung2020-04-032-0/+84
| * cmp2lut: comment out unused since 362f4f9Eddie Hung2020-04-031-8/+8
* | Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-0216-387/+387
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| * | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-0216-366/+366
| * | kernel: use more ID::*Eddie Hung2020-04-025-26/+26
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* / simcells.v: Generate the fine FF cell types by a python script.Marcin Kościelnicki2020-04-022-19/+270
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* Fix indentation in `techlibs/ice40/synth_ice40.cc`.Alberto Gonzalez2020-04-011-4/+4
* Merge pull request #1794 from YosysHQ/dave/mince-abc9-fixDavid Shah2020-03-211-0/+1
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| * ice40: Map unmapped 'mince' DFFs to gate levelDavid Shah2020-03-201-0/+1
* | ice40: Fix typos in SPRAM ABC9 timing specsSylvain Munaut2020-03-201-2/+2
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* xilinx: Mark IOBUFDS.IOB as external padMarcin Kościelnicki2020-03-202-1/+2
* ice40: Fix SPRAM model to keep data stable if chipselect is lowSylvain Munaut2020-03-141-5/+8
* Fix invalid verilog syntaxMiodrag Milanovic2020-03-141-1/+1
* Merge pull request #1716 from zeldin/ecp5_fixN. Engelhardt2020-03-091-2/+0
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| * remove unused parametersN. Engelhardt2020-03-061-3/+0
| * ecp5: Add missing parameter to \$__ECP5_PDPW16KDMarcus Comstedt2020-02-221-0/+1
* | ice40: fix specify for ICE40_{LP,U}Eddie Hung2020-03-051-4/+4
* | ice40: fix implicit signal in specify, also clamp negative times to 0Eddie Hung2020-03-041-22/+22
* | Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1Eddie Hung2020-03-044-109/+244
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| * | xilinx: consider DSP48E1.ADREGEddie Hung2020-03-044-5/+8
| * | xilinx: cleanup DSP48E1 handling for abc9Eddie Hung2020-03-043-86/+125
| * | xilinx: improve specify for DSP48E1Eddie Hung2020-03-041-32/+116
| * | xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.vEddie Hung2020-03-042-5/+14
* | | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-032-6/+39
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| * | Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-282-6/+39
* | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-0230-1440/+2803
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| * | | Remove RAMB{18,36}E1 from cells_xtra.pyEddie Hung2020-02-271-2/+2
| * | | xilinx: Update RAMB* specify entriesEddie Hung2020-02-271-11/+42
| * | | ice40: add delays to SB_CARRYEddie Hung2020-02-271-0/+30
| * | | xilinx: add delays to INVEddie Hung2020-02-271-0/+3
| * | | More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
| * | | Make +/xilinx/cells_sim.v legalEddie Hung2020-02-271-76/+78
| * | | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-273-530/+496
| * | | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-7/+10
| * | | Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happyEddie Hung2020-02-271-14/+12
| * | | ice40: fix specify for inverted clocksEddie Hung2020-02-271-27/+27
| * | | Fix tests by gating some specify constructs from iverilogEddie Hung2020-02-271-0/+16
| * | | abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-271-2/+6
| * | | ice40: specify fixesEddie Hung2020-02-273-66/+66
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