| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
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| | * | | | use ADDSUB ALU mode to remove inverters | Pepijn de Vos | 2019-10-21 | 2 | -7/+77 | |
| | * | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-10-21 | 58 | -1315/+24105 | |
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| | * | | | | remove duplicate DFFR | Pepijn de Vos | 2019-10-16 | 1 | -10/+0 | |
| | * | | | | Revert "add MUX support" | Pepijn de Vos | 2019-09-06 | 3 | -17/+0 | |
| | * | | | | fix BRAM width and init | Pepijn de Vos | 2019-09-06 | 2 | -12/+28 | |
| | * | | | | add more DFF to sim lib | Pepijn de Vos | 2019-09-06 | 2 | -6/+111 | |
| | * | | | | WIP aditional DFF primitives | Pepijn de Vos | 2019-09-05 | 2 | -1/+48 | |
| | * | | | | support bram initialisation | Pepijn de Vos | 2019-09-05 | 5 | -3/+25 | |
| | * | | | | use singleton ground and vcc nets, apparently this makes pnr happier | Pepijn de Vos | 2019-09-05 | 1 | -1/+1 | |
| | * | | | | add MUX support | Pepijn de Vos | 2019-09-05 | 3 | -0/+17 | |
| | * | | | | set undriven pads to zero | Pepijn de Vos | 2019-09-04 | 1 | -0/+1 | |
| | * | | | | Merge remote-tracking branch 'diego/gowin' | Pepijn de Vos | 2019-09-04 | 2 | -2/+2 | |
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| | | * | | | | Updating gowin | Diego H | 2019-09-02 | 2 | -2/+2 | |
| | * | | | | | gowin: add splitnets to appease the PnR | Pepijn de Vos | 2019-09-04 | 1 | -0/+1 | |
| * | | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*. | Marcin Kościelnicki | 2019-11-19 | 3 | -132/+516 | |
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| * | | | | | ecp5: Use new autoname pass for better cell/net names | David Shah | 2019-11-15 | 1 | -0/+1 | |
| * | | | | | Merge pull request #1490 from YosysHQ/clifford/autoname | Clifford Wolf | 2019-11-14 | 1 | -0/+1 | |
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| | * | | | | | Add "autoname" pass and use it in "synth_ice40" | Clifford Wolf | 2019-11-13 | 1 | -0/+1 | |
| * | | | | | | Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim | Clifford Wolf | 2019-11-14 | 1 | -14/+436 | |
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| | * | | | | | ice40: Add post-pnr ICESTORM_RAM model and fix FFs | David Shah | 2019-10-23 | 1 | -2/+340 | |
| | * | | | | | ice40: Support for post-pnr timing simulation | David Shah | 2019-10-23 | 1 | -12/+96 | |
| * | | | | | | Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp | Clifford Wolf | 2019-11-11 | 1 | -1/+1 | |
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| * | | | | | synth_xilinx: Merge blackbox primitive libraries. | Marcin Kościelnicki | 2019-11-06 | 11 | -23234/+29820 | |
| * | | | | | xilinx: Add URAM288 mapping for xcup | David Shah | 2019-10-23 | 5 | -2/+92 | |
| * | | | | | xilinx: Add support for UltraScale[+] BRAM mapping | David Shah | 2019-10-23 | 7 | -416/+1062 | |
| * | | | | | xilinx: Support multiplier mapping for all families. | Marcin Kościelnicki | 2019-10-22 | 9 | -9/+269 | |
| * | | | | | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg | Clifford Wolf | 2019-10-22 | 2 | -0/+2 | |
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| | * | | | | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 2 | -0/+2 | |
| * | | | | | ecp5: Pass -nomfs to abc9 | David Shah | 2019-10-20 | 1 | -2/+2 | |
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| * | | | | Makefile: don't assume python is called `python3` | Sean Cross | 2019-10-19 | 4 | -6/+6 | |
| * | | | | Merge branch 'master' into mmicko/efinix | Miodrag Milanović | 2019-10-18 | 37 | -474/+305 | |
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| | * | | | ecp5: Add ECLKBRIDGECS blackbox | David Shah | 2019-10-11 | 1 | -0/+7 | |
| | * | | | ecp5: Add attrmvcp to copy syn_useioff to driving FF | David Shah | 2019-10-10 | 1 | -0/+1 | |
| | * | | | ecp5: Set syn_useioff on IO FFs to enable packing | David Shah | 2019-10-10 | 1 | -8/+8 | |
| | * | | | xilinx: Add simulation model for IBUFG. | Marcin Kościelnicki | 2019-10-10 | 5 | -33/+14 | |
| | * | | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 31 | -228/+236 | |
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| | | * \ \ | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 4 | -181/+9 | |
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| | | * | | | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 31 | -227/+235 | |
| | * | | | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 | |
| | * | | | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
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| | * | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -2/+6 | |
| | * | | | | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 3 | -178/+2 | |
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| | * | | | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 5 | -31/+4 | |
| | * | | | Oops | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
| | * | | | Ohmilord this wasn't added all this time!?! | Eddie Hung | 2019-10-04 | 1 | -0/+29 | |
| * | | | | FF should be initialized to 0 | Miodrag Milanovic | 2019-10-04 | 1 | -1/+3 | |
| * | | | | Add missing latch mapping | Miodrag Milanovic | 2019-10-04 | 1 | -0/+12 | |
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| * | | | ecp5: Fix shuffle_enable port | David Shah | 2019-10-01 | 1 | -2/+2 | |
| * | | | ecp5: Add support for mapping 36-bit wide PDP BRAMs | David Shah | 2019-10-01 | 6 | -1/+183 | |
| * | | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 6 | -122/+46 | |
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index : iCE40/yosys | |
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