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* intel_alm: fix DFFE matchingDan Ravensloft2020-06-111-1/+1
* Do not optimize away FFs in "prep" and Verific fron-endClaire Wolf2020-06-091-2/+2
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-1/+1
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| * abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-291-1/+1
* | Add flooring division operatorXiretza2020-05-282-0/+71
* | Add flooring modulo operatorXiretza2020-05-282-3/+124
* | xilinx: tidy up cells_sim.v a littleEddie Hung2020-05-251-5/+7
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* ecp5: cleanup unused +/ecp5/abc9_model.vEddie Hung2020-05-233-14/+0
* Add force_downto and force_upto wire attributes.Marcelina Koƛcielnicka2020-05-1939-24/+232
* abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_Eddie Hung2020-05-142-14/+2
* abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove itEddie Hung2020-05-142-5/+4
* abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-142-7/+5
* Cleanup; reduce Module::derive() callsEddie Hung2020-05-142-4/+4
* ecp5: latches_map.v if *not* -asyncprldEddie Hung2020-05-141-2/+2
* ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.vEddie Hung2020-05-144-43/+3
* ecp5: fix rebase mistakeEddie Hung2020-05-141-3/+3
* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
* abc9: only do +/abc9_map if `DFFEddie Hung2020-05-141-0/+2
* ecp5: TRELLIS_FF bypass path only in async modeEddie Hung2020-05-141-8/+8
* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-143-4/+4
* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-143-4/+198
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-148-763/+129
* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-142-10/+26
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-144-4/+3
* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-144-0/+55
* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-141-4/+0
* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
* Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"Eddie Hung2020-05-143-220/+64
* ecp5: (* abc9_flop *) gated behind YOSYSEddie Hung2020-05-141-0/+2
* ecp5: add synth_ecp5 -dff to work with -abc9Eddie Hung2020-05-142-12/+47
* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
* ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-initEddie Hung2020-05-143-64/+220
* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-142-8/+41
* ice40: split out cells_map.v into ff_map.vEddie Hung2020-05-143-31/+29
* synth_xilinx: rename dff_mode -> dffEddie Hung2020-05-141-8/+10
* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-145-369/+5
* Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-142-7/+30
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| * techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-052-7/+30
* | ice40: fix ICESTORM_LC process sensitivityEddie Hung2020-05-121-1/+1
* | ice40: fix whitespaceEddie Hung2020-05-121-15/+14
* | ecp5: Add missing SERDES parametersDavid Shah2020-05-121-0/+4
* | intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-078-52/+143
* | synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-043-11/+34
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* gowin,ecp5: remove generated files in `make clean`.whitequark2020-04-242-2/+10
* intel_alm: cleanup duplicationDan Ravensloft2020-04-245-113/+64
* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+10
* ecp5: ecp5_gsr to skip cells that don't have GSR parameter againEddie Hung2020-04-221-1/+1
* xilinx: improve xilinx_dffopt messageEddie Hung2020-04-221-3/+6
* Cleanup use of hard-coded default parameters in light of #1945Eddie Hung2020-04-222-12/+6
* intel_alm: Documentation improvementsDan Ravensloft2020-04-213-14/+127