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Author
Age
Files
Lines
*
Rename "fine:" label to "map:" in "synth_ice40"
Clifford Wolf
2018-12-16
1
-1
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+1
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Merge pull request #724 from whitequark/equiv_opt
Clifford Wolf
2018-12-16
1
-0
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+2
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equiv_opt: pass -D EQUIV when techmapping.
whitequark
2018-12-07
1
-0
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+2
*
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Merge pull request #730 from smunaut/ffssr_dont_touch
Clifford Wolf
2018-12-16
1
-0
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+3
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ice40: Honor the "dont_touch" attribute in FFSSR pass
Sylvain Munaut
2018-12-08
1
-0
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+3
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Merge pull request #725 from olofk/ram4k-init
Clifford Wolf
2018-12-16
1
-0
/
+19
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Only use non-blocking assignments of SB_RAM40_4K for yosys
Olof Kindgren
2018-12-06
1
-0
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+19
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synth_ice40: split `map_gates` off `fine`.
whitequark
2018-12-06
1
-0
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+4
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synth_ice40: add -noabc option, to use built-in LUT techmapping.
whitequark
2018-12-05
1
-2
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+16
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gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
whitequark
2018-12-05
2
-0
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+88
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Fix typo.
whitequark
2018-12-05
1
-2
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+2
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Merge pull request #713 from Diego-HR/master
Clifford Wolf
2018-12-05
5
-12
/
+91
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Changes in GoWin synth commands and ALU primitive support
Diego H
2018-12-03
5
-12
/
+91
*
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Merge pull request #712 from mmicko/anlogic-support
Clifford Wolf
2018-12-05
7
-0
/
+1278
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Leave only real black box cells
Miodrag Milanovic
2018-12-02
1
-312
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+0
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Initial support for Anlogic FPGA
Miodrag Milanovic
2018-12-01
7
-0
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+1590
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opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
whitequark
2018-12-05
1
-2
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+2
*
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synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
whitequark
2018-12-05
1
-1
/
+13
*
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Extract ice40_unlut pass from ice40_opt.
whitequark
2018-12-05
3
-13
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+109
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ice40: Add option to only use CE if it'd be use by more than X FFs
Sylvain Munaut
2018-11-27
1
-0
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+14
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Merge pull request #697 from eddiehung/xilinx_ps7
Clifford Wolf
2018-11-12
2
-0
/
+624
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Add support for Xilinx PS7 block
Eddie Hung
2018-11-10
2
-0
/
+624
*
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Merge pull request #695 from daveshah1/ecp5_bb
Clifford Wolf
2018-11-12
2
-1
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+420
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ecp5: Add 'fake' DCU parameters
David Shah
2018-11-09
1
-0
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+11
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ecp5: Add blackboxes for ancillary DCU cells
David Shah
2018-11-09
1
-0
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+18
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ecp5: Adding some blackbox cells
David Shah
2018-11-07
2
-1
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+391
*
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Fix sf2 LUT interface
Clifford Wolf
2018-10-31
2
-12
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+12
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Basic SmartFusion2 and IGLOO2 synthesis support
Clifford Wolf
2018-10-31
5
-0
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+377
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ecp5: Remove DSP parameters that don't work
David Shah
2018-10-22
1
-21
/
+0
*
ecp5: Add DSP blackboxes
David Shah
2018-10-21
3
-1
/
+118
*
ecp5: Sim model fixes
David Shah
2018-10-19
1
-3
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+5
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ecp5: Add latch inference
David Shah
2018-10-19
3
-3
/
+12
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Merge pull request #657 from mithro/xilinx-vpr
Clifford Wolf
2018-10-18
1
-3
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+2
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xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
Tim 'mithro' Ansell
2018-10-08
1
-3
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+2
*
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ecp5: Disable LSR inversion
David Shah
2018-10-16
2
-21
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+21
*
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BRAM improvements
David Shah
2018-10-12
1
-11
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+16
*
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ecp5: Adding BRAM maps for all size options
David Shah
2018-10-10
1
-1
/
+64
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ecp5: First BRAM type maps successfully
David Shah
2018-10-10
8
-10
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+76
*
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ecp5: Script for BRAM IO connections
David Shah
2018-10-10
4
-64
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+115
*
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ecp5: Adding BRAM initialisation and config
David Shah
2018-10-09
5
-0
/
+73
*
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ecp5: Add blackbox for DP16KD
David Shah
2018-10-05
1
-0
/
+93
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Add inout ports to cells_xtra.v
Clifford Wolf
2018-10-04
2
-2
/
+14
*
xilinx: Adding missing inout IO port to IOBUF
Tim Ansell
2018-10-03
1
-0
/
+1
*
Merge pull request #645 from daveshah1/ecp5_dram_fix
Clifford Wolf
2018-10-02
1
-0
/
+1
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ecp5: Don't map ROMs to DRAM
David Shah
2018-10-01
1
-0
/
+1
*
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Add iCE40 SB_SPRAM256KA simulation model
Clifford Wolf
2018-09-10
1
-9
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+30
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Consistent use of 'override' for virtual methods in derived classes.
Henner Zeller
2018-07-20
16
-54
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+54
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ecp5: Fixing miscellaneous sim model issues
David Shah
2018-07-16
1
-2
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+2
*
ecp5: Fixing 'X' issues with LUT simulation models
David Shah
2018-07-16
1
-6
/
+19
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ecp5: ECP5 synthesis fixes
David Shah
2018-07-16
3
-15
/
+32
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