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* Rename "fine:" label to "map:" in "synth_ice40"Clifford Wolf2018-12-161-1/+1
* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-161-0/+2
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| * equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-071-0/+2
* | Merge pull request #730 from smunaut/ffssr_dont_touchClifford Wolf2018-12-161-0/+3
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| * | ice40: Honor the "dont_touch" attribute in FFSSR passSylvain Munaut2018-12-081-0/+3
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* | Merge pull request #725 from olofk/ram4k-initClifford Wolf2018-12-161-0/+19
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| * | Only use non-blocking assignments of SB_RAM40_4K for yosysOlof Kindgren2018-12-061-0/+19
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* / synth_ice40: split `map_gates` off `fine`.whitequark2018-12-061-0/+4
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* synth_ice40: add -noabc option, to use built-in LUT techmapping.whitequark2018-12-051-2/+16
* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-052-0/+88
* Fix typo.whitequark2018-12-051-2/+2
* Merge pull request #713 from Diego-HR/masterClifford Wolf2018-12-055-12/+91
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| * Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-035-12/+91
* | Merge pull request #712 from mmicko/anlogic-supportClifford Wolf2018-12-057-0/+1278
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| * | Leave only real black box cellsMiodrag Milanovic2018-12-021-312/+0
| * | Initial support for Anlogic FPGAMiodrag Milanovic2018-12-017-0/+1590
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* | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-2/+2
* | synth_ice40: add -relut option, to run ice40_unlut and opt_lut.whitequark2018-12-051-1/+13
* | Extract ice40_unlut pass from ice40_opt.whitequark2018-12-053-13/+109
* | ice40: Add option to only use CE if it'd be use by more than X FFsSylvain Munaut2018-11-271-0/+14
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* Merge pull request #697 from eddiehung/xilinx_ps7Clifford Wolf2018-11-122-0/+624
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| * Add support for Xilinx PS7 blockEddie Hung2018-11-102-0/+624
* | Merge pull request #695 from daveshah1/ecp5_bbClifford Wolf2018-11-122-1/+420
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| * ecp5: Add 'fake' DCU parametersDavid Shah2018-11-091-0/+11
| * ecp5: Add blackboxes for ancillary DCU cellsDavid Shah2018-11-091-0/+18
| * ecp5: Adding some blackbox cellsDavid Shah2018-11-072-1/+391
* | Fix sf2 LUT interfaceClifford Wolf2018-10-312-12/+12
* | Basic SmartFusion2 and IGLOO2 synthesis supportClifford Wolf2018-10-315-0/+377
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* ecp5: Remove DSP parameters that don't workDavid Shah2018-10-221-21/+0
* ecp5: Add DSP blackboxesDavid Shah2018-10-213-1/+118
* ecp5: Sim model fixesDavid Shah2018-10-191-3/+5
* ecp5: Add latch inferenceDavid Shah2018-10-193-3/+12
* Merge pull request #657 from mithro/xilinx-vprClifford Wolf2018-10-181-3/+2
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| * xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
* | ecp5: Disable LSR inversionDavid Shah2018-10-162-21/+21
* | BRAM improvementsDavid Shah2018-10-121-11/+16
* | ecp5: Adding BRAM maps for all size optionsDavid Shah2018-10-101-1/+64
* | ecp5: First BRAM type maps successfullyDavid Shah2018-10-108-10/+76
* | ecp5: Script for BRAM IO connectionsDavid Shah2018-10-104-64/+115
* | ecp5: Adding BRAM initialisation and configDavid Shah2018-10-095-0/+73
* | ecp5: Add blackbox for DP16KDDavid Shah2018-10-051-0/+93
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* Add inout ports to cells_xtra.vClifford Wolf2018-10-042-2/+14
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
* Merge pull request #645 from daveshah1/ecp5_dram_fixClifford Wolf2018-10-021-0/+1
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| * ecp5: Don't map ROMs to DRAMDavid Shah2018-10-011-0/+1
* | Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-2016-54/+54
* ecp5: Fixing miscellaneous sim model issuesDavid Shah2018-07-161-2/+2
* ecp5: Fixing 'X' issues with LUT simulation modelsDavid Shah2018-07-161-6/+19
* ecp5: ECP5 synthesis fixesDavid Shah2018-07-163-15/+32
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