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* Adjusting Vivado's BRAM min bits threshold for RAMB18E1Diego H2019-11-271-2/+5
* xilinx: Add simulation models for IOBUF and OBUFT.Marcin Kościelnicki2019-11-263-25/+30
* clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-1/+5
* xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-251-2/+6
* coolrunner2: remove spurious log_pop() call, fixes #1463Martin Pietryka2019-11-231-2/+0
* gowin: Add missing .gitignore entriesMarcin Kościelnicki2019-11-221-0/+2
* Merge pull request #1449 from pepijndevos/gowinClifford Wolf2019-11-198-43/+547
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| * Remove dff init altogetherPepijn de Vos2019-11-192-3/+3
| * add help for nowidelut and abc9 optionsPepijn de Vos2019-11-181-1/+7
| * Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-164-15/+439
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| * | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-4/+4
| * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-1122-22988/+30572
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| * | | fix wide lutsPepijn de Vos2019-11-061-12/+12
| * | | add IOBUFPepijn de Vos2019-10-282-1/+10
| * | | add tristate buffer and testPepijn de Vos2019-10-282-2/+8
| * | | More formattingPepijn de Vos2019-10-281-55/+49
| * | | really really fix formatting maybePepijn de Vos2019-10-281-41/+41
| * | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
| * | | add wide lutsPepijn de Vos2019-10-283-36/+119
| * | | add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
| * | | ALU sim tweaksPepijn de Vos2019-10-241-11/+11
| * | | add a few more missing dffPepijn de Vos2019-10-211-7/+16
| * | | add negedge DFFPepijn de Vos2019-10-212-15/+139
| * | | use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
| * | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-10-2158-1315/+24105
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| * | | | remove duplicate DFFRPepijn de Vos2019-10-161-10/+0
| * | | | Revert "add MUX support"Pepijn de Vos2019-09-063-17/+0
| * | | | fix BRAM width and initPepijn de Vos2019-09-062-12/+28
| * | | | add more DFF to sim libPepijn de Vos2019-09-062-6/+111
| * | | | WIP aditional DFF primitivesPepijn de Vos2019-09-052-1/+48
| * | | | support bram initialisationPepijn de Vos2019-09-055-3/+25
| * | | | use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
| * | | | add MUX supportPepijn de Vos2019-09-053-0/+17
| * | | | set undriven pads to zeroPepijn de Vos2019-09-041-0/+1
| * | | | Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
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| | * | | | Updating gowinDiego H2019-09-022-2/+2
| * | | | | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
* | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
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* | | | | ecp5: Use new autoname pass for better cell/net namesDavid Shah2019-11-151-0/+1
* | | | | Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-141-0/+1
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| * | | | | Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
* | | | | | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
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| * | | | | ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| * | | | | ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
* | | | | | Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
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* | | | | synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
* | | | | xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-235-2/+92
* | | | | xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-237-416/+1062
* | | | | xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-229-9/+269
* | | | | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-222-0/+2
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