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* Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-201-1/+1
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| * Fixed small typo in ice40_unlut help summaryacw12512019-06-191-1/+1
| * Fixed the help summary line for a few commandsacw12512019-06-191-1/+1
* | Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abcEddie Hung2019-06-201-0/+1
* | Really permute Xilinx LUT mappings as default LUT6.I5:A6Eddie Hung2019-06-181-16/+16
* | Revert "Fix (do not) permute LUT inputs, but permute mux selects"Eddie Hung2019-06-181-33/+31
* | Clean upEddie Hung2019-06-181-6/+4
* | Fix (do not) permute LUT inputs, but permute mux selectsEddie Hung2019-06-181-31/+33
* | Fix copy-pasta issueEddie Hung2019-06-171-9/+8
* | Permute INIT for +/xilinx/lut_map.vEddie Hung2019-06-171-32/+58
* | Simplify commentEddie Hung2019-06-171-1/+1
* | Update LUT7/8 delays to take account for [ABC]OUTMUX delayEddie Hung2019-06-171-5/+5
* | Try -W 300Eddie Hung2019-06-171-1/+2
* | Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> OEddie Hung2019-06-151-2/+2
* | As per @daveshah1 remove async DFF timing from xilinxEddie Hung2019-06-141-2/+2
* | Resolve comments from @daveshah1Eddie Hung2019-06-141-1/+1
* | Add XC7_WIRE_DELAY macro to synth_xilinx.ccEddie Hung2019-06-141-1/+3
* | Update delays based on SymbiFlow/prjxray-dbEddie Hung2019-06-141-12/+13
* | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}Eddie Hung2019-06-144-3/+3
* | Comment out dist RAM boxing on ECP5 for nowEddie Hung2019-06-141-1/+1
* | Remove WIP ABC9 flop supportEddie Hung2019-06-144-46/+46
* | Make doc consistentEddie Hung2019-06-143-3/+6
* | ecp5: Add abc9 optionDavid Shah2019-06-146-70/+184
* | Fix name clashEddie Hung2019-06-131-4/+8
* | Fix LP SB_LUT4 timingEddie Hung2019-06-131-1/+1
* | Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-06-121-0/+8
* | Reduce diff with masterEddie Hung2019-06-121-1/+1
* | Remove abc_flop{,_d} attributes from ice40/cells_sim.vEddie Hung2019-06-121-40/+20
* | Fix spacingEddie Hung2019-06-121-6/+6
* | Remove wide mux inferenceEddie Hung2019-06-124-194/+3
* | Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
* | Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
* | Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-111-1/+1
* | Disable dist RAM boxes due to comb loopEddie Hung2019-06-111-2/+2
* | Remove #ifndef ABCEddie Hung2019-06-111-4/+0
* | Revert "Revert "Move ff_map back after ABC for shregmap""Eddie Hung2019-06-101-5/+5
* | Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"Eddie Hung2019-06-101-2/+2
* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-101-0/+24
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| * ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4kSimon Schubert2019-06-101-0/+24
* | Comment out muxpack (currently broken)Eddie Hung2019-06-071-2/+2
* | $__XILINX_MUX_ -> $__XILINX_SHIFTXEddie Hung2019-06-062-11/+11
* | Fix muxcover and its techmappingEddie Hung2019-06-062-3/+3
* | Run muxpack and muxcover in synth_xilinxEddie Hung2019-06-062-1/+18
* | Remove abc_flop attributes for nowEddie Hung2019-06-061-56/+10
* | Merge remote-tracking branch 'origin/eddie/muxpack' into xc7muxEddie Hung2019-06-061-0/+15
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| * Merge pull request #1073 from whitequark/ecp5-diamond-iobDavid Shah2019-06-061-0/+15
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| | * ECP5: implement all Diamond I/O buffer primitives.whitequark2019-06-061-0/+15
* | | Update abc attributes on FD*E_1Eddie Hung2019-06-051-6/+26
* | | CleanupEddie Hung2019-06-052-17/+0
* | | Call shregmap -tech xilinx_staticEddie Hung2019-06-051-1/+1
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