| Commit message (Expand) | Author | Age | Files | Lines |
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| * | xilinx: Update RAMB* specify entries | Eddie Hung | 2020-02-27 | 1 | -11/+42 |
| * | xilinx: add delays to INV | Eddie Hung | 2020-02-27 | 1 | -0/+3 |
| * | Make +/xilinx/cells_sim.v legal | Eddie Hung | 2020-02-27 | 1 | -76/+78 |
| * | Get rid of (* abc9_{arrival,required} *) entirely | Eddie Hung | 2020-02-27 | 3 | -530/+496 |
| * | abc9_ops: use TimingInfo for -prep_{lut,box} too | Eddie Hung | 2020-02-27 | 1 | -7/+10 |
| * | Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy | Eddie Hung | 2020-02-27 | 1 | -14/+12 |
| * | Fix tests by gating some specify constructs from iverilog | Eddie Hung | 2020-02-27 | 1 | -0/+16 |
| * | abc9_ops: ignore (* abc9_flop *) if not '-dff' | Eddie Hung | 2020-02-27 | 1 | -2/+6 |
| * | Update xilinx for ABC9 | Eddie Hung | 2020-02-27 | 3 | -20/+16 |
| * | Fix commented out specify statement | Eddie Hung | 2020-02-27 | 1 | -6/+6 |
| * | xilinx: improve specify functionality | Eddie Hung | 2020-02-27 | 5 | -446/+519 |
| * | xilinx: use specify blocks in place of abc9_{arrival,required} | Eddie Hung | 2020-02-27 | 1 | -176/+404 |
| * | Auto-generate .box/.lut files from specify blocks | Eddie Hung | 2020-02-27 | 7 | -426/+151 |
| * | abc9_ops: -prep_box, to be called once | Eddie Hung | 2020-02-27 | 1 | -1/+1 |
| * | abc9_ops: -prep_lut and -write_lut to auto-generate LUT library | Eddie Hung | 2020-02-27 | 2 | -4/+85 |
| * | xilinx: mark IOBUFDSE3 IOB pin as external | Piotr Binkowski | 2020-02-27 | 2 | -1/+2 |
| * | abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr | Eddie Hung | 2020-02-13 | 1 | -11/+12 |
| * | abc9: cleanup | Eddie Hung | 2020-02-10 | 1 | -40/+40 |
| * | Remove unnecessary comma | Eddie Hung | 2020-02-07 | 1 | -3/+2 |
| * | xilinx: Add support for LUT RAM on LUT4-based devices. | Marcin Kościelnicki | 2020-02-07 | 4 | -27/+22 |
| * | xilinx: Initial support for LUT4 devices. | Marcin Kościelnicki | 2020-02-07 | 3 | -53/+152 |
| * | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. | Marcin Kościelnicki | 2020-02-07 | 11 | -1/+370 |
| * | xilinx: Add support for Spartan 3A DSP block RAMs. | Marcin Kościelnicki | 2020-02-07 | 3 | -1/+39 |
| * | Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk | Eddie Hung | 2020-02-06 | 1 | -4/+5 |
| * | Fix/cleanup +/xilinx/arith_map.v | Eddie Hung | 2020-02-06 | 1 | -111/+44 |
| * | Merge pull request #1661 from YosysHQ/eddie/abc9_required | Eddie Hung | 2020-02-05 | 5 | -142/+375 |
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| | * | Merge branch 'eddie/abc9_refactor' into eddie/abc9_required | Eddie Hung | 2020-01-27 | 3 | -126/+89 |
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| | * \ | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req... | Eddie Hung | 2020-01-15 | 1 | -1/+1 |
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| | * | | | abc9_ops: generate flop box ids, add abc9_required to FD* cells | Eddie Hung | 2020-01-14 | 1 | -12/+45 |
| | * | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req... | Eddie Hung | 2020-01-14 | 2 | -13/+20 |
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| | * \ \ \ | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req... | Eddie Hung | 2020-01-12 | 1 | -1/+0 |
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| | | * | | | | Fix abc9_xc7.box comments | Eddie Hung | 2020-01-07 | 1 | -7/+14 |
| | | * | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs | Eddie Hung | 2020-01-07 | 6 | -155/+645 |
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| | | * | | | | | Re-enable &mfs for synth_{ecp5,xilinx} | Eddie Hung | 2020-01-06 | 1 | -1/+0 |
| | * | | | | | | Add abc9_required to DSP48E1.{A,B,C,D,PCIN} | Eddie Hung | 2020-01-10 | 1 | -38/+117 |
| | * | | | | | | abc9_ops -prep_times: generate flop boxes from abc9_required attr | Eddie Hung | 2020-01-10 | 1 | -61/+0 |
| | * | | | | | | Add abc9_ops -check, -prep_times, -write_box for required times | Eddie Hung | 2020-01-10 | 1 | -0/+5 |
| | * | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req... | Eddie Hung | 2020-01-08 | 5 | -1676/+518 |
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| | * \ \ \ \ \ \ | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into xaig_arrival_r... | Eddie Hung | 2020-01-06 | 6 | -498/+1003 |
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| | * | | | | | | | | Consistency | Eddie Hung | 2019-12-27 | 1 | -1/+1 |
| | * | | | | | | | | Update some abc9_arrival times, add abc9_required times | Eddie Hung | 2019-12-27 | 3 | -24/+220 |
| * | | | | | | | | | Add opt_lut_ins pass. (#1673) | Marcelina Kościelnicka | 2020-02-03 | 1 | -0/+1 |
| * | | | | | | | | | xilinx: use RAM32M/RAM64M for memories with two read ports | Marcin Kościelnicki | 2020-02-02 | 1 | -2/+2 |
| * | | | | | | | | | synth_xilinx: cleanup help | Eddie Hung | 2020-01-28 | 1 | -6/+4 |
| * | | | | | | | | | synth_xilinx: fix help when no active_design; fixes #1664 | Eddie Hung | 2020-01-28 | 1 | -2/+3 |
| * | | | | | | | | | xilinx: Add simulation model for DSP48 (Virtex 4). | Marcin Kościelnicki | 2020-01-29 | 6 | -45/+534 |
| * | | | | | | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts | Eddie Hung | 2020-01-28 | 1 | -62/+37 |
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| | * | | | | | | | | | xilinx/ice40/ecp5: undo permuting LUT masks in lut_map | Eddie Hung | 2020-01-27 | 1 | -62/+37 |
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| * | | | | | | | | | Fix unresolved conflict from #1573 | Eddie Hung | 2020-01-28 | 1 | -1/+1 |
| * | | | | | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate | N. Engelhardt | 2020-01-28 | 1 | -0/+3 |
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