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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-10 11:45:41 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-10 11:45:41 -0800 |
| commit | b2259a920165930261050065d870d03fc7573346 (patch) | |
| tree | 39cf41ae134935fd673944e2742f38d0ecc9ac9d /techlibs/xilinx | |
| parent | 5e280a3b591d3d8b556992b0708fcaaf6a6a3e0d (diff) | |
| download | yosys-b2259a920165930261050065d870d03fc7573346.tar.gz yosys-b2259a920165930261050065d870d03fc7573346.tar.bz2 yosys-b2259a920165930261050065d870d03fc7573346.zip | |
Add abc9_ops -check, -prep_times, -write_box for required times
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 204fa883f..25530acf8 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -33,6 +33,11 @@ endmodule module \$__ABC9_FF_ (input D, output Q); endmodule +(* abc9_box_id = (9000+DELAY) *) +module \$__ABC9_DELAY (input I, output O); + parameter DELAY = 0; +endmodule + // Box to emulate async behaviour of FDC* (* abc9_box_id = 1000, lib_whitebox *) module \$__ABC9_ASYNC0 (input A, S, output Y); |